View MT47H64M8_873511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by micron without notice. 512mb: x4, x8, x16 ddr2 sdram features pdf: 09005aef8117c18e/source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_1.fm - rev. k 8/06 en 1 ?2004 micron technology, inc. all rights reserved. ddr2 sdram mt47h128m4 ? 32 meg x 4 x 4 banks MT47H64M8 ? 16 meg x 8 x 4 banks mt47h32m16 ? 8 meg x 16 x 4 banks for the latest data sheet, refer to micron?s web site: http://www.micron.com/ddr2 features ?rohs compliant ?v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v ? jedec standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? 4-bit prefetch architecture ? duplicate output strobe (rdqs) option for x8 ? dll to align dq and dqs transitions with ck ? 4 internal banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency ? 1 t ck ? programmable burst lengths: 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? industrial temperature (it) option ? supports jedec clock jitter specification options marking ? configuration 128 meg x 4 (32 meg x 4 x 4 banks) 128m4 64 meg x 8 (16 meg x 8 x 4 banks) 64m8 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 ? fbga package (lead-free) 84-ball fbga (12mm x 12.5mm) (:b) (10mm x 12.5mm) (:d) cc bn 60-ball fbga (12mm x 10mm) (:b) (10mm x 10mm) (:d) cb b6 ? timing ? cycle time 5.0ns @ cl = 3 (ddr2-400) -5e 3.75ns @ cl = 4 (ddr2-533) -37e 3.0ns @ cl = 5 (ddr2-667) -3 3.0ns @ cl = 4 (ddr2-667) -3e 2.5ns @ cl = 6 (ddr2-800) -25 2.5ns @ cl = 5 (ddr2-800) -25e ? self refresh standard none low-power l ? operating temperature commercial (0c t c 85c) none industrial (?40c t c 95c; ?40c t a 85c) it ? revision :a/:b/:d table 1: configuration addressing architecture 128 meg x 4 64 meg x 8 32 meg x 16 configuration 32 meg x 4 x 4 banks 16 meg x 8 x 4 banks 8 meg x 16 x 4 banks refresh count 8k 8k 8k row addr. 16k (a0?a13) 16k (a0?a13) 8k (a0?a12) bank addr. 4 (ba0?ba1) 4 (ba0?ba1) 4 (ba0?ba1) column addr. 2k (a0?a9, a11) 1k (a0?a9) 1k (a0?a9) note: cl = cas latency. table 2: key timing parameters speed grade data rate (mhz) t rcd (ns) t rp (ns) t rc (ns) cl = 3 cl = 4 cl = 5 cl = 6 -5e 400 400 n/a n/a 15 15 55 -37e 400 533 n/a n/a 15 15 55 -3 400 533 667 n/a 15 15 55 -3e n/a667667n/a121254 -25 n/a n/a 667 800 15 15 55 -25e n/a 533 800 n/a 12.5 12.5 55
pdf: 09005aef8117c18e/source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2toc.fm - rev. k 8/06 en 2 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 industrial temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 ball assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 mode register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 write recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 extended mode register (emr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 dqs# enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 rdqs enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 output enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 on-die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 off-chip driver (ocd) impedance calibratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 posted cas additive latency (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 extended mode register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 extended mode register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 command truth tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 deselect, nop, and lm commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 load mode (lm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 active command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 active operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 precharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 self refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 precharge power-down clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
pdf: 09005aef8117c18e/source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2toc.fm - rev. k 8/06 en 3 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram table of contents reset function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 (cke low anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 odt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 mrs command to odt update delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 temperature and thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 ac and dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 input electrical characteristics and operat ing conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 input slew rate derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 power and ground clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ac overshoot/undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 output electrical charac teristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 full strength pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 full strength pull-up driver characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 reduced strength pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 reduced strength pull-up driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 fbga package capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 i dd 7 conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ac operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
pdf: 09005aef8117c18e/source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2lof.fm - rev. k 8/06 en 4 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram list of figures list of figures figure 1: 512mb ddr2 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: 84-ball fbga (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 3: 60-ball fbga (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: functional block diagra m ? 32 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 5: functional block diagra m ? 64 meg x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 6: functional block diagra m ? 128 meg x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7: ddr2 power-up and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8: mode register (mr) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 9: cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 10: extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 11: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 12: write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13: extended mode register 2 (emr2) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 14: extended mode register 3 (emr3) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 15: active command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 16: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 17: example: meeting t rrd (min) and t rcd (min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 18: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 19: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 20: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 21: read interrupted by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 22: read-to-precharge ? bl = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 23: read-to-precharge ? bl = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 24: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 25: bank read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 26: bank read ? with auto precharg e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 27: x4, x8 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 28: x16 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 29: data output timing ? t ac and t dqsck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 30: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 31: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 32: consecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 33: nonconsecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 34: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 35: write interrupted by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 36: write-to-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 37: write-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 38: bank write ? without auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 39: bank write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 40: write ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 41: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 42: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 43: self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 44: refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 45: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 46: read to power-down or self refresh entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 47: read with auto precharge to powe r-down or self refresh entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 48: write to power-down or self-refresh entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 49: write with auto precharge to po wer-down or self refresh entry . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 50: refresh command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 51: active command to power-down en try . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 52: precharge command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 53: load mode command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 54: input clock frequency change du ring precharge power-down mode . . . . . . . . . . . . . . . . . . . . . . . .71 figure 55: reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 56: odt timing for entering and exiting power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
pdf: 09005aef8117c18e/source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2lof.fm - rev. k 8/06 en 5 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram list of figures figure 57: timing for mrs command to odt update delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 58: odt timing for active or fast-e xit power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 59: odt timing for slow-exit or pr echarge power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 60: odt turn-off timings when enteri ng power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 61: odt turn-on timing when entering power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 62: odt turn-off timing when exitin g power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 63: odt turn-on timing when exiting power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 64: example temperature test point location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 65: single-ended input signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 66: differential input signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 67: nominal slew rate for t is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 68: tangent line for t is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 69: nominal slew rate for t ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 figure 70: tangent line for t ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 figure 71: nominal slew rate for t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 72: tangent line for t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 73: nominal slew rate for t dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 figure 74: tangent line for t dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 75: ac input test signal waveform command/address balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 76: ac input test signal waveform for data with dqs, dq s# (differential) . . . . . . . . . . . . . . . . . . . . . 102 figure 77: ac input test signal waveform for data with dqs (sin gle-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 figure 78: ac input test signal waveform (d ifferential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 79: input clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 80: overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 81: undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 82: differential output si gnal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 83: output slew rate load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 84: full strength pull-down characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 85: full strength pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 86: reduced strength pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 87: reduced strength pull-up charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 88: 84-ball fbga package ? 12mm x 12.5mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 89: 84-ball fbga package ? 10mm x 12.5mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 90: 60-ball fbga package ? 12mm x 10mm (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 91: 60-ball fbga package ? 10mm x 10mm (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
pdf: 09005aef8117c18e/source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2lot.fm - rev. k 8/06 en 6 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram list of tables list of tables table 1: configuration addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: fbga 84-/60-ball descriptions ? 128 meg x 4, 64 meg x 8, 32 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . .1 1 table 4: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 5: truth table ? ddr2 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 6: truth table ? current state bank n - command to bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 7: truth table ? current state bank n - command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 8: minimum delay with auto precharge enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 9: read using concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 10: write using concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 11: cke truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 12: ddr2-400/533 odt timing for acti ve and fast-exit power-down modes . . . . . . . . . . . . . . . . . . . . .76 table 13: ddr2-400/533 odt timing for sl ow-exit and precharge power-down modes . . . . . . . . . . . . . . . . .77 table 14: ddr2-400/533 odt turn-off timings when entering po wer-down mode . . . . . . . . . . . . . . . . . . . . .78 table 15: ddr2-400/533 odt turn-on timing when entering power-down mode . . . . . . . . . . . . . . . . . . . . . .79 table 16: ddr2-400/533 odt turn-off timing when exiting power- down mode . . . . . . . . . . . . . . . . . . . . . . .80 table 17: ddr2-400/533 odt turn-on timing when exiting power- down mode . . . . . . . . . . . . . . . . . . . . . . .81 table 17: absolute maximum dc ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 18: temperature limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 19: thermal impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 20: recommended dc operating conditions (sstl_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table 21: odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table 22: input dc logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 table 23: input ac logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 table 24: differential input logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table 25: ac input test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 26: ddr2-400/533 setup and hold time derating values ( t is and t ih) . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 27: ddr2-667 setup and hold time derating values ( t is and t ih) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 28: ddr2-400/533 t ds, t dh derating values with differential strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 29: ddr2-667 t ds, t dh derating values with differential strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 30: single-ended dqs slew rate derating values using t ds b and t dh b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 table 31: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-667 . . . . . . . . . . . . . . . . . . .96 table 32: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-533 . . . . . . . . . . . . . . . . . . .97 table 33: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-400 . . . . . . . . . . . . . . . . . . .97 table 34: input clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 35: address and control balls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 36: clock, data, strobe, and mask balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 37: differential ac output parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 38: output dc current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 39: output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 40: full strength pull-down current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 41: full strength pull-up current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 42: reduced strength pull-down current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 43: reduced strength pull-up current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 44: input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 45: ddr2 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 46: general i dd parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 47: i dd 7 timing patterns (4-bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 49: ac operating conditions for -25e and -25 speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 7 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram part numbers part numbers figure 1: 512mb ddr2 part numbers note: not all speeds and configur ations are available. contact mi cron sales for current revision. fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part numb er. micron?s fbga part marking decoder is available at www.micron.com/decoder. general description the 512mb ddr2 sdram is a high-speed cmos, dynamic random access memory containing 536,870,912 bits. it is internally co nfigured as a 4-bank dram. the functional block diagrams of the all device configurat ions are shown in ?functional description? on page 14. ball assignments and signal descriptions are shown in ?ball assignment and description? on page 9. the 512mb ddr2 sdram uses a double data ra te architecture to achieve high-speed operation. the double data rate architecture is essentially a 4 n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o balls. a single read or write access for the 512mb ddr2 sdram effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o balls. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte (ldqs, ld qs#) and one for the upper byte (udqs, udqs#). package 84-ball 12 x 12.5 fbga 84-ball 10 x 12.5 fbga 6 0-ball 12 x 10 fbga 6 0-ball 10 x 10 fbga cc bn c b b 6 example part number: MT47H64M8bt-37e :a configuration 128 me g x 4 6 4 me g x 8 32 me g x 1 6 128m4 6 4m8 32m1 6 speed grade t c k = 5ns, c l = 3 t c k = 3.75ns, c l = 4 t c k = 3ns, c l = 5 t c k = 3ns, c l = 4 t c k = 2.5ns, c l = 6 t c k = 2.5ns, c l = 5 -5e -37e -3 -3e -25 -25e - c onfi g uration mt47h pa c ka g e s pee d revision revision :a/:b/:d : low-power industrial temperature l it {
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 8 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram general description the 512mb ddr2 sdram operates from a differ ential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs as well as to both edges of ck. read and write accesses to the ddr2 sdram are burst-oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or wr ite command are used to select the bank and the starting column location for the burst access. the ddr2 sdram provides for programmable read or write burst lengths of four or eight locations. ddr2 sdram supports interrup ting a burst read of eight with another read or a burst write of eight with another write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdrams, the pipelined, multibank architecture of ddr2 sdrams allows for concurrent operation, thereby pr oviding high, effective bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power-saving, power-down mode. all inputs are compatible with the jedec st andard for sstl_18. all full drive-strength outputs are sstl_ 18-compatible. industrial temperature the industrial temperature (it) device has two simultaneous requirements: ambient temperature surrounding the device cannot exceed ?40c or +85c, and the case temperature cannot exceed ?40c or 95c. jedec specifications require the refresh rate to double when t c exceeds 85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when the t c is < 0c or > 85c. general notes ? the functionality and the timi ng specifications discussed in this data sheet are for the dll-enabled mode of operation. ? throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated otherwise. additionally, the x 16 is divided into 2 bytes, the lower byte and upper byte. for the lower byte (dq0?dq7), dm refers to ldm and dqs refers to ldqs. for the upper byte (dq8?dq15), dm refers to udm and dqs refers to udqs. ? complete functionality is described th roughout the document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes precedence over a general statement.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 9 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ball assignment and description ball assignment and description figure 2: 84-ball fbga (x16) 12mm x 12.5mm and 10mm x 12.5mm (top view) 1234 6789 5 v dd dq14 v dd q dq12 v dd dq6 v dd q dq4 v dd l rfu v ss v dd nc v ss q dq9 v ss q nc v ss q dq1 v ss q v ref cke ba0 a10 a3 a7 a12 v ss udm v dd q dq11 v ss ldm v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q udqs v dd q dq10 v ss q ldqs v dd q dq2 v ss dl ras# cas# a2 a6 a11 rfu v dd q dq15 v dd q dq13 v dd q dq7 v dd q dq5 v dd odt v dd v ss udqs#/nu v ss q dq8 v ss q ldqs#/nu v ss q dq0 v ss q ck ck# cs# a0 a4 a8 rfu a b c d e f g h j k l m n p r
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 10 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ball assignment and description figure 3: 60-ball fbga (x4, x8) 12mm x 10mm and 10mm x 10mm (top view) 1234 6789 5 v dd nf, dq6 v dd q nf, dq4 v dd l rfu v ss v dd nf, rdqs#/nu v ss q dq1 v ss q v ref cke ba0 a10 a3 a7 a12 v ss dm, dm/rdqs v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q dqs v dd q dq2 v ss dl ras# cas# a2 a6 a11 rfu v dd q nf, dq7 v dd q nf, dq5 v dd odt v dd v ss dqs#/nu v ss q dq0 v ss q ck ck# cs# a0 a4 a8 a13 a b c d e f g h j k l
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 11 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ball assignment and description table 3: fbga 84-/60-ball descriptions ? 128 meg x 4, 64 meg x 8, 32 meg x 16 x16 fbga ball number x4, x8 fbga ball number symbol type description k9 f9 odt input on-die termination: odt (registered hi g h) enables termination resistance internal to the ddr2 sd ram. when enabled, odt is only applied to each of the following balls: dq0?dq15, ldm, udm, ldqs, ldqs#, udqs, and udqs# for the x 16; dq0?dq7, dqs, dqs#, rdqs, rdqs#, and dm for the x8; dq0?dq3, dqs, dqs#, and dm for the x4. the odt input will be ignored if disabled via the load mode command. j8, k8 e8, f8 ck, ck# input clock: ck and ck# are differential clock in puts. all address and control input sign als are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/ dqs#) is referenced to th e crossings of ck and ck#. k2 f2 cke input clock enable: cke (registered hi g h) activates and cke (registered low) deactivates clocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down mode an d self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power- down entry, power-down exit, output disable, and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once v dd is applied during first power-up. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for prope r self refresh operation, v ref must be maintained. l8 g 8 cs# input chip select: cs# enables (registere d low) and disables (registered hi g h) the command decoder. all commands are masked when cs# is registered hi g h. cs# provides for external bank selection on systems with multiple ranks. cs# is considered pa rt of the command code. k7, l7, k3 f7, g 7, f3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. f3, b3 b3 ldm, udm (dm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is concurrently sampled hi g h during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loadin g is designed to match that of dq and dqs balls. ldm is dm fo r lower byte dq0?dq7 and udm is dm for upper byte dq8?dq15. l2, l3 g 2, g 3 ba0?ba1 input bank address inputs: ba0?ba1 define to which bank an active, read, write, or prechar g e command is being applied. ba0? ba1define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. m8, m3, m7, n2, n8, n3, n7, p2, p8, p3, m2, p7, r2 ?a0?a3 a4?a7 a8?a11 a12 input address inputs: provid e the row address for active commands, and the column address and auto prec harge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a prechar g e command determines whether the prechar g e applies to one bank (a10 low, bank selected by ba1?ba0) or all banks (a10 hi g h). the address inputs also provide the op-code during a load mode command.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 12 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ball assignment and description ? h8, h3, h7, j2, j8, j3, j7, k2, k8, k3, h2, k7, l2, l8 a0?a3 a4?a7 a8?a11 a12?a13 input address inputs: provid e the row address for active commands and the column address and auto prec harge bit (a10) for read/write commands to select one location out of the memory array in the respective bank. a10 sampled during a prechar g e command determines whether the prechar g e applies to one bank (a10 low, bank selected by ba1?ba0) or all banks (a10 hi g h). the address inputs also provide the op-code during a load mode command. g 8, g 2, h7, h3, h1, h9, f1, f9, c8, c2, d7, d3, d1, d9, b1, b9 ?dq0?dq3 dq4?dq7 dq8?dq11 dq12?dq15 i/o data input/output: bidirectional data bus for 32 meg x 16. ? c8, c2, d7, d3, d1, d9, b1, b9 dq0?dq3 dq4?dq7 i/o data input/output: bidirectional data bus for 64 meg x 8. ? c8,c2,d7,d3 dq0?dq3 i/o data input/output: bidirectional data bus for 128 meg x 4. b7 a8 ? udqs, udqs# i/o data strobe for upper byte: outp ut with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. udqs# is only used when differential data strobe mo de is enabled via the load mode command. f7 e8 ? ldqs, ldqs# i/o data strobe for lower byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. ldqs# is only used when differential data strobe mode is enabled via the load mode command. ? b7, a8 dqs, dqs# i/o data strobe: output with read data, input with write data for source synchronous operation. edge -aligned with read data, center aligned with write data. dqs# is on ly used when differential data strobe mode is enabled vi a the load mode command. ?b3 a2 rdqs, rdqs# output redundant data strobe for 64 meg x 8 only. rdqs is enabled/ disabled via the lo ad mode command to the extended mode register (emr). when rdqs is enab led, rdqs is output with read data only and is ignored during wr ite data. when rdqs is disabled, ball b3 becomes data mask (see dm ball). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. a1, e1, m9, j9, r1 a1, e9, h9, l1 v dd supply power supply: 1.8v 0.1v. j1 e1 v dd l supply dll power supply: 1.8v 0.1v. a9, c1, c3, c7, c9, e9, g 1, g 3, g 7, g 9 a9, c1, c3, c7, c9 v dd q supply dq power supply: 1.8v 0.1v. isol ated on the device for improved noise immunity. j2 e2 v ref supply sstl_18 reference voltage. a3, e3, j3, n1, p9 a3, e3, j1, k9 v ss supply g round. j7 e7 v ss dl supply dll ground. isolated on the device from v ss and v ss q. a7, b2, b8, d2, d8, e7, f2, f8, h2, h8 a7, b2, b8, d2, d8 v ss q supply dq ground. isolated on the device for improved noise immunity. a2, e2 ? nc ? no connect: these balls sh ould be left unconnected. ? b1, d1, d9, b9 nf ? no function: these balls are used as dq4?dq7 on the 64 meg x 8, but are nf (no function) on the 128 meg x 4 configuration. table 3: fbga 84-/60-ball descriptions ? 128 meg x 4, 64 meg x 8, 32 meg x 16 (continued) x16 fbga ball number x4, x8 fbga ball number symbol type description
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 13 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ball assignment and description a8, e8 ? nu ? not used: not used only on x16. if emr[e10] = 0, a8 and e8 are udqs# and ldqs#. if emr[e10] = 1, then a8 and e8 are not used. ? a2, a8 nu ? not used: not used only on x8. if emr[e10] = 0, a2 and a8 are rdqs# and dqs#. if emr[e10] = 1, then a2 and a8 are not used. l1, r3, r7, r8 ? rfu ? reserved for future use (x16 only ): row address bits a13 (r8), a14 (r3), and a15 (r7) are reserved for 2 g b and 4 g b densities. ba2 (l1) is reserved for 1 g b device. ? g 1, l3, l7 rfu ? reserved for future use (x4, x8 onl y): row address bits a14 (l3) and a15 (l7) are reserved for 2 g b and 4 g b densities. ba2 ( g 1) is reserved for 1 g b device. table 3: fbga 84-/60-ball descriptions ? 128 meg x 4, 64 meg x 8, 32 meg x 16 (continued) x16 fbga ball number x4, x8 fbga ball number symbol type description
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 14 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram functional description functional description the 512mb ddr2 sdram is a high-speed cmos dynamic random access memory containing 536,870,912 bits. the 512mb ddr2 sdram is internally configured as a 4- bank dram. the 512mb ddr2 sdram uses a double data ra te architecture to achieve high-speed operation. the ddr2 architecture is essentially a 4 n -prefetch architecture, with an inter- face designed to transfer two data words per clock cycle at the i/o balls. a single read or write access for the 512mb ddr2 sdram consists of a single 4 n -bit-wide, one-clock- cycle data transfer at the internal dram core and four corresponding n -bit- wide, one- half-clock-cycle data transfers at the i/o balls. prior to normal operation, the ddr2 sdram mu st be initialized. th e following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. figure 4: functional block diagram ? 32 meg x 16 13 row- addre ss mux c ontrol logi c c olumn- addre ss c ounter/ lat c h mode regi s ter s 10 a0?a12, ba0, ba1 13 addre ss regi s ter 15 25 6 (x 6 4) 1 6 ,384 i/o gating dm ma s k logi c c olumn de c oder bank 0 memory array (8,192 x 128 x 6 4) bank 0 row- addre ss lat c h& de c oder 8,192 s en s e amplifier s bank c ontrol logi c 15 bank 1 bank 2 bank 3 13 8 2 2 refre s h c ounter 1 6 1 6 1 6 4 6 4 6 4 6 4 c k out data udq s , udq s # ldq s , ldq s # internal c k, c k# c k, c k# c ol0, c ol1 c ol0, c ol1 c k in dll mux dq s generator 1 6 1 6 1 6 1 6 1 6 udq s , udq s # ldq s , ldq s # 4 read lat c h write fifo & driver s data 1 6 1 6 1 6 1 6 6 4 2 2 2 2 ma s k 2 2 2 2 2 8 1 6 1 6 2 bank 1 bank 2 bank 3 input regi s ter s udm, ldm dq0?dq15 ra s # c a s # c k cs # we# c k# c ommand de c ode c ke odt drvr s r c vr s v dd q r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt c ontrol sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 15 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram functional description figure 5: functional block diagram ? 64 meg x 8 figure 6: functional block diagram ? 128 meg x 4 14 row- addre ss mux c ontrol logi c c olumn- addre ss c ounter/ lat c h mode regi s ter s 10 c ommand de c ode a0?a13, ba0, ba1 14 addre ss regi s ter 1 6 25 6 (x32) 8,192 i/o gating dm ma s k logi c c olumn de c oder bank 0 memory array (1 6 ,384 x 25 6 x 32) bank 0 row- addre ss lat c h & de c oder 1 6 ,384 s en s e amplifier s bank c ontrol logi c 1 6 bank 1 bank 2 bank 3 14 8 2 2 refre s h c ounter 8 8 8 2 r c vr s 32 32 32 c k out data dq s , dq s # internal c k, c k# c k, c k# c ol0, c ol1 c ol0, c ol1 c k in drvr s dll mux dq s generator 8 8 8 8 8 dq0?dq7 dq s , dq s # 2 read lat c h write fifo & driver s data 8 8 8 8 32 1 1 1 1 ma s k 1 1 1 1 1 4 8 8 2 bank 1 bank 2 bank 3 input regi s ter s dm rdq s # ra s # c a s # c k cs # we# c k# c ke odt rdq s v dd q r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt c ontrol sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 14 row- addre ss mux c ontrol logi c c olumn- addre ss c ounter/ lat c h mode regi s ter s 11 c ommand de c ode a0?a13, ba0, ba1 14 addre ss regi s ter 1 6 512 (x1 6 ) 8,192 i/o gating dm ma s k logi c c olumn de c oder bank0 memory array (1 6 ,384 x 512 x 1 6 ) bank0 row- addre ss lat c h & de c oder 1 6 ,384 s en s e amplifier s bank c ontrol logi c 1 6 bank1 bank2 bank3 14 9 2 2 refre s h c ounter 4 4 4 2 r c vr s 1 6 1 6 1 6 c k out data dq s , dq s # internal c k, c k# c k, c k# c ol0, c ol1 c ol0, c ol1 c k in drvr s dll mux dq s generator 4 4 4 4 4 dq0?dq3 dq s , dq s # 2 read lat c h write fifo & driver s data 4 4 4 4 1 6 1 1 1 1 ma s k 1 1 1 1 1 4 4 4 2 bank1 bank2 bank3 input regi s ter s dm ra s # c a s # c k cs # we# c k# c ke odt v dd q r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt c ontrol sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 16 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram initialization initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. figu re 7 illustrates the sequence required for power-up and initialization. figure 7: ddr2 power-up and initialization notes appear on page 17 lv c mo s low level 2 t vtd 1 c ke r tt power-up: v dd an d sta b le c lo c k ( c k, c k#) t = 200s (min) hi g h-z dm 4 dq s 4 hi g h-z addre ss 3 c k c k# t c l v tt 1 v ref v dd q c ommand 3 nop 5 pre t0 ta0 don?t c are t c l t c k v dd odt dq 4 hi g h-z t = 400ns (min) 6 t b 0 200 c y c les of c k are re q uire d b efore a read c omman d c an b e issue d . mr with dll re s et t rf c lm 10 pre 11 lm 9 ref 12 ref lm 13 t g 0 th0 ti0 tj0 mr without dll re s et emr with o c d default tk0 tl0 tm0 te0 tf0 emr(2) emr(3) t mrd lm 8 lm 7 a10 = 1 t rpa t c 0t d 0 ss tl_18 low level 2 valid 1 6 valid in d i c ates a b reak in time s c ale lm 14 emr with o c d exit lm 15 normal operation see note 12 c ode c ode a10 = 1 c ode c ode c ode c ode c ode t mrd t mrd t mrd t mrd t rpa t rf c v dd l t mrd t mrd emr
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 17 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram initialization notes: 1. applying power; if cke is maintained below 0.2 x v dd q, outputs remain disabled. to guaran- tee r tt (odt resistance) is off, v ref must be valid and a low le vel must be applied to the odt ball (all other inputs may be undefined; i/os and outputs must be less than v dd q dur- ing voltage ramp time to avoid ddr2 sdram device latch-up). v tt is not applied directly to the device; however, t v tt should be 0 to avoid device latch-up. at least one of the follow- ing two sets of conditions (a or b) must be met to obtain a stable supply state (stable supply defined as v dd , v dd l, v dd q, v ref , and v tt are between their minimum and maximum val- ues as stated in table 20 on page 84): a. single power source: the v dd voltage ramp from 300mv to v dd (min) must take no longer than 200ms; during the v dd voltage ramp, |v dd - v dd q| 0.3v. once supply voltage ramping is complete (when v dd q crosses v dd [min]), table 20 specifications apply. ? v dd , v dd l, and v dd q are driven from a sing le power converter output ? v tt is limited to 0.95v max ? v ref tracks v dd q/2; v ref must be within 0.3v with respect to v dd q/2 during sup- ply ramp time ? v dd q v ref at all times b. multiple power sources: v dd v dd l v dd q must be maintained during supply volt- age ramping, for both ac and dc levels, until supply voltage ramping completes (v dd q crosses v dd [min]). once supply voltage ramping is complete, table 20 specifications apply. ? apply v dd and v dd l before or at the same time as v dd q; v dd /v dd l voltage ramp time must be 200ms from when v dd ramps from 300mv to v dd (min) ? apply v dd q before or at the same time as v tt ; the v dd q voltage ramp time from when v dd (min) is achieved to when v dd q (min) is achieved must be 500ms; while v dd is ramping, current can be supplied from v dd through the device to v dd q ? v ref must track v dd q/2; v ref must be within 0.3 v with respect to v dd q/2 during supply ramp time; v dd q v ref must be met at all times ? apply v tt ; the v tt voltage ramp time from when v dd q (min) is achieved to when v tt (min) is achieved must be no greater than 500ms 2. cke uses lvcmos input levels prior to state t0 to ensure dqs are high-z during device power-up prior to v ref being stable. after state t0, cke is required to have sstl_18 input levels. once cke transitions to a high level, it must stay hi g h for the duration of the initial- ization sequence. 3. pre = prechar g e command, lm = load mode command, mr = mode register, emr = extended mode register, emr2 = extended mode register 2, emr3 = extended mode regis- ter 3, ref = refresh command, ac t = active command, a10 = prechar g e all, code = desired values for mode registers (bank addres ses are required to be decoded), valid - any valid command/address, ra = row address, bank address. 4. dm represents dm for x4, x8 configurations and udm, ldm for x16 configuration; dqs rep- resents dqs, dqs#, udqs, udqs #, ldqs, ldqs#, rdqs, rdqs# for the appropriate configu- ration (x4, x8, x16); dq represents dq0?dq3 for x4, dq?dq7 for x8, and dq0?dq15 for x16. 5. for a minimum of 200s after stable power and clock (ck, ck#), apply nop or deselect commands, then take cke hi g h. 6. wait a minimum of 400ns, then issue a prechar g e all command. 7. issue a load mode co mmand to the emr(2). (to issue an emr(2) command, provide low to ba0, and provide hi g h to ba1.) set register e7 to ?0? or ?1;? all others must be ?0.? 8. issue a load mode co mmand to the emr(3). (to issue an emr(3) command, provide hi g h to ba0 and ba1.) set all registers to ?0.? 9. issue a load mode comma nd to the emr to enable dll. to issue a dll enable command, provide low to ba1 and a0; provide hi g h to ba0. bits e7, e8, and e9 can be set to ?0? or ?1;? micron recommends setting them to ?0.? 10. issue a load mode comma nd for dll reset. 200 cycles of clock input is required to lock the dll. (to issue a dll reset, provide hi g h to a8 and provide low to ba1 and ba0.) cke must be hi g h the entire time. 11. issue prechar g e all command. 12. issue two or more refresh commands.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 18 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram initialization 13. issue a load mode comma nd with low to a8 to initialize device operation (i.e., to pro- gram operating parameters without resetting the dll). to access the mode registers, ba1 =1, ba0 = 0. 14. issue a load mode comma nd to the emr to enable ocd defa ult by setting bits e7, e8, and e9 to ?1,? and then setting all other desired parameters. to access the extended mode reg- ister, ba1 = 0, ba0 = 1. 15. issue a load mode command to the emr to enab le ocd exit by setting bits e7, e8, and e9 to ?0,? and then setting all other desired pa rameters. to access the extended mode regis- ters, ba1 = 0, ba0 = 1. 16. the ddr2 sdram is now initialized and ready for normal operation 20 0 clock cycles after the dll reset at tf0. it is also suggested to include a single dummy write command fol- lowed by t wr anytime after the refresh commands, but before the first true write com- mand to the dram.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 19 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) mode register (mr) the mode register is used to define the sp ecific mode of operation of the ddr2 sdram. this definition includes the selection of a burst length, burst type, cas latency, oper- ating mode, dll reset, write recovery, and power-down mode, as shown in figure 8 on page 20. contents of the mode register can be altered by re-executing the load mode (lm) command. if the user chooses to modify only a subset of the mr variables, all vari- ables (m0?m13 for x4 and x8 or m0?m12 for x16) must be programmed when the command is issued. the mr is programmed via the lm command (b its ba1?ba0 = 0, 0) and other bits (m13? m0 for x4 and x8, m12?m0 for x16) will retain the stored information until it is programmed again or the device loses power (except for bit m8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. the lm command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in prog ress. the controller must wait the specified time t mrd before initiating any subsequent op erations such as an active command. violating either of these requirements will result in unspecified operation. burst length burst length is defined by bits m0?m3, as shown in figure 8 on page 20. read and write accesses to the ddr2 sdram are burst-oriented, with the burst length being program- mable to either four or eight. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a2?a i when bl = 4 and by a3?a i when bl = 8 (where a i is the most significant column address bit for a given configuration). the remaining (least signifi- cant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 20 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) figure 8: mode register (mr) definition notes: 1. m13 (a13) is reserved for future use and must be programmed to ?0.? a13 is not used in x16 configuration. 2. not all listed cl options are supp orted in any indivi dual speed grade. burst type accesses within a given burst may be programmed to be either sequential or interleaved. the burst type is selected via bit m3, as shown in figure 8. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in table 4 on page 21. ddr2 sdram supports 4-bit burst mode and 8- bit burst mode only. for 8-bit burst mode, full, interleaved address ordering is supported; however, sequential address ordering is nibble-based. burst length cas# bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 97 6 543 8 210 a10 a12 a11 ba0 ba1 10 11 12 13 0 1 14 bur s t length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 bur s t type sequential interleaved m3 ca s laten c y (cl) reserved reserved reserved 3 4 5 6 reserved m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m 6 0 0 0 0 1 1 1 1 0 1 mo d e normal test m7 15 dll tm 0 1 dll re s et no yes m 8 write recovery reserved 2 3 4 5 6 reserved reserved m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr a13 mr 0 1 0 1 mo d e regi s ter definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 m12 0 1 pd mo d e fast exit (normal) slow exit (low power) m14 latency
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 21 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) operating mode the normal operating mode is selected by issuing a command with bit m7 set to ?0,? and all other bits set to the desired values, as shown in figure 8 on page 20. when bit m7 is ?1,? no other bits of the mode register are programmed. programming bit m7 to ?1? places the ddr2 sdram into a test mode that is only used by the manufacturer and should not be used. no operation or functional ity is guaranteed if m7 bit is ?1.? dll reset dll reset is defined by bit m8, as shown in figure 8 on page 20. programming bit m8 to ?1? will activate the dll reset function. bi t m8 is self-clearing, meaning it returns back to a value of ?0? after the dll reset function has been issued. anytime the dll reset function is used, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchroniz ation to occur may result in a violation of the t ac or t dqsck parameters. write recovery write recovery (wr) time is defined by bi ts m9?m11, as shown in figure 8 on page 20. the wr register is used by the ddr2 sdram during write with auto precharge opera- tion. during write with auto precharge operation, the ddr2 sdram delays the internal auto precharge operation by wr cl ocks (programmed in bits m9?m11) from the last data burst. an example of write with auto precharge is shown in figure 39 on page 57. wr values of 2, 3, 4, 5, or 6 clocks may be used for programming bits m9?m11. the user is required to program the value of wr, which is calculated by dividing t wr (in nanosec- onds) by t ck (in nanoseconds) and rounding up a noninteger value to the next integer; wr [cycles] = t wr [ns] / t ck [ns]. reserved states should not be used as unknown opera- tion or incompatibility with future versions may result. table 4: burst definition burst length starting column address (a2, a1, a0) order of accesses within a burst burst type = sequential burst type = interleaved 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 22 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram mode register (mr) power-down mode active power-down (pd) mode is defined by bit m12, as shown in figure 8 on page 20. pd mode allows the user to determine the active power-down mode, which determines performance versus power savings. pd mode bit m12 does not apply to precharge pd mode. when bit m12 = 0, standard active pd mode, or ?fast-exit? active pd mode, is enabled. the t xard parameter is used for fast-exit active pd exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower-power active pd mode, or ?slow-exit? active pd mode, is enabled. the t xards parameter is used for slow-exit active pd exit timing. the dll can be enabled but ?frozen? during active pd mode since the exit-to-read command timing is relaxed. the power difference expected between pd normal and pd low-power mode is defined in the i dd table. cas latency (cl) the cas latency (cl) is defined by bits m4 ?m6, as shown in figure 8 on page 20. cl is the delay, in clock cycles, between the regi stration of a read command and the avail- ability of the first bit of outp ut data. the cl can be set to 3, 4, 5, or 6 clocks, depending on the speed grade option being used. ddr2 sdram does not support any half-clock latencies. reserved states should not be used as unknown operation or incompatib ility with future versions may result. ddr2 sdram also supports a feature called posted cas additive latency (al). this feature allows the read command to be issued prior to t rcd (min) by delaying the internal command to the ddr2 sdram by al clocks. the al feature is described in more detail in ?posted cas additive latency (al)? on page 26. examples of cl = 3 and cl = 4 are shown in figure 9 on page 23; both assume al = 0. if a read command is registered at clock edge n , and the cl is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes al = 0).
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 23 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram extended mode register (emr) figure 9: cas latency (cl) notes: 1. bl = 4. 2. posted cas# additive latency (al) = 0. 3. shown with nominal t ac, t dqsck, and t dqsq. extended mode register (emr) the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, on- die termination (odt) (r tt ), posted al, off-chip driver impedance calibration (ocd), dqs# enable/disable, rdqs/rdqs# enable/disable, and output disable/enable. these functions are controlled via the bits shown in figure 10 on page 24. the emr is programmed via the lm command and will re tain the stored information until it is programmed again or the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. the emr must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requiremen ts could result in unspecified operation. d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read t0 t1 t2 don?t care transitionin g data nop nop nop d out n t3 t4 t5 nop nop t6 nop d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop d out n t3 t4 t5 nop nop t6 nop
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 24 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram dll enable/disable figure 10: extended mode register definition notes: 1. during initialization, all th ree bits must be set to ?1? for ocd default state, then must be set to ?0? before initialization is finish ed, as detailed in the notes on pages 17?18. 2. e13 (a13) is not used on the x16 configuration. dll enable/disable the dll may be enabled or disabled by programming bit e0 during the lm command, as shown in figure 10. the dll must be enab led for normal operation. dll enable is required during power-up initialization an d upon returning to normal operation after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using the lm command. the dll is automatically disabled when ente ring self refresh operation and is auto- matically re-enabled and reset upon exit of self refresh operation. anytime the dll is enabled (and subsequently reset), 200 cloc k cycles must occur before a read command can be issued, to allow time for the internal clock to synchronize with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. dll posted cas# out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 97 6 543 8 210 a10 a12 a11 ba0 ba1 10 11 12 13 0 2 14 po s te d ca s # a dd itive laten c y (al) 0 1 2 3 4 reserved reserved reserved e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll ena b le enable (normal) disable (test/debug) e0 15 0 1 rdq s ena b le no yes e11 ocd program a13 ods r tt dqs# 0 1 dq s # ena b le enable disable e10 rdqs rtt (nominal) r tt disabled 75 150 50 e2 0 1 0 1 e 6 0 0 1 1 0 1 outputs enabled disabled e12 0 1 0 1 mo d e regi s ter s et mode register set (mrs) extended mode register (emrs) extended mode register (emrs2) extended mode register (emrs3) e15 0 0 1 1 e14 mrs ocd operation ocd not supported 1 reserved reserved reserved ocd default state 1 e7 0 1 0 0 1 e 8 0 0 1 0 1 e9 0 0 0 1 1 0 1 output drive s trength e1 full strength (18 target) reduced strength (40 target) r tt
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 25 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram output drive strength output drive strength the output drive strength is defined by bit e1, as shown in figure 10 on page 24. the normal drive strength for all outputs are sp ecified to be sstl_18. programming bit e1 = 0 selects normal (full strength) drive strength for all outputs. selecting a reduced drive strength option (e1 = 1) will reduce all outputs to approximately 60 percent of the sstl_18 drive strength. this option is intend ed for the support of lighter load and/or point-to-point environments. dqs# enable/disable the dqs# ball is enabled by bit e10. when e10 = 0, dqs# is the complement of the differential data strobe pair dqs/dqs#. when disabled (e10 = 1), dqs is used in a single-ended mode and the dqs# ball is disabled. when disabled, dqs# should be left floating. this function is also used to enable/disable rdqs#. if rdqs is enabled (e11 = 1) and dqs# is enabled (e10 = 0), then both dqs# and rdqs# will be enabled. rdqs enable/disable the rdqs ball is enabled by bit e11, as shown in figure 10 on page 24. this feature is only applicable to the x8 configuration. when enabled (e11 = 1), rdqs is identical in function and timing to data strobe dqs during a read. during a write operation, rdqs is ignored by the ddr2 sdram. output enable/disable the output enable function is defined by bit e12, as shown in figure 10 on page 24. when enabled (e12 = 0), all outputs (dqs, dqs, dqs#, rdqs, rdqs#) function normally. when disabled (e12 = 1), all ddr2 sdram outputs (dqs, dqs, dqs#, rdqs, rdqs#) are disabled, thus removing output bu ffer current. the output disable feature is intended to be used during i dd characterization of read current. on-die termination (odt) odt effective resistance, r tt (eff), is defined by bits e2 and e6 of the emr, as shown in figure 10 on page 24. the odt feature is desi gned to improve signal integrity of the memory channel by allowing the ddr2 sdram controller to independently turn on/off odt for any or all devices. r tt effective resistance values of 50 , 75 , and 150 are selectable and apply to each dq, dqs/dqs#, rdqs/rdqs#, udqs/udqs#, ldqs/ ldqs#, dm, and udm/ldm signals. bits (e 6, e2) determine what odt resistance is enabled by turning on/off ?sw1,? ?sw2,? or ?sw3.? the odt effective resistance value is selected by enabling switch ?sw1,? wh ich enables all r1 values that are 150 each, enabling an effectiv e resistance of 75 (r tt 2 ( eff ) = r2/2). similarly, if ?sw2? is enabled, all r2 values that are 300 each, enable an effective odt resistance of 150 (r tt 2 ( eff ) = r2/2). switch ?sw3? enables r1 values of 100 , enabling effective resistance of 50 . reserved states should not be used, as unknown operation or incompatibility with future versions may result. the odt control ball is used to determine when r tt (eff) is turned on and off, assuming odt has been enable d via bits e2 and e6 of the emr. the odt feature and odt input ball are only used during active, active power-down (both fast-exit and slow- exit modes), and precharge power-down modes of operation. odt must be turned off prior to entering self refresh. during powe r-up and initialization of the ddr2 sdram, odt should be disabled until issuing the emr command to enable the odt feature, at
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 26 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram off-chip driver (ocd) impedance calibration which point the odt ball will determine the r tt (eff) value. any time the emr enables the odt function, odt may not be driven hi gh until eight clocks after the emr has been enabled. see ?odt timing? on page 74 for odt timing diagrams. off-chip driver (ocd) impedance calibration the off-chip driver function is no longer supported and must be set to the default state. see ?initialization? on page 16 for proper setting of ocd defaults. posted cas additi ve latency (al) posted cas additive latency (al) is supported to make the command and data bus effi- cient for sustainable bandwidths in ddr2 sdram. bits e3?e5 define the value of al, as shown in figure 10 on page 24. bits e3?e5 allow the user to program the ddr2 sdram with an inverse al of 0, 1, 2, 3, or 4 clocks. reserved states should not be used as unknown operation or incompatibility with future versions may result. in this operation, the ddr2 sdram allows a read or write command to be issued prior to t rcd (min) with the requirement that al t rcd (min). a typical application using this feature would set al = t rcd (min) - 1 x t ck. the read or write command is held for the time of the al before it is issued internally to the ddr2 sdram device. rl is controlled by the sum of al and cl; rl = al + cl. write latency (wl) is equal to rl minus one clock; wl = al + cl - 1 x t ck. an example of rl is shown in figure 11. an example of a wl is shown in figure 12 on page 27. figure 11: read latency notes: 1. bl = 4. 2. shown with nominal t ac, t dqsck, and t dqsq. 3. cl = 3. 4. al = 2. 5. rl = al +cl = 5. d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# al = 2 active n t0 t1 t2 don?t care transitionin g data read n nop nop d out n t3 t4 t5 nop t6 nop t7 t8 nop nop cl = 3 rl = 5 t rcd (min) nop
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 27 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram extended mode register 2 figure 12: write latency notes: 1. bl = 4. 2. cl = 3. 3. al = 2. 4. wl = al + cl - 1 = 4. extended mode register 2 the extended mode register 2 (emr2) controls functions beyond those controlled by the mode register. currently all bits in emr2 are reserved, except for e7, which is for commercial or high-temperature operations, as shown in figure 13. the emr2 is programmed via the lm command and will re tain the stored information until it is programmed again or the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. bit e7 (a7) must be programmed as ?1? to provide a faster refresh rate on it devices if the t case exceeds 85c. emr2 must be loaded when all banks are id le and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requiremen ts could result in unspecified operation. figure 13: extended mode register 2 (emr2) definition notes: 1. e13 (a13)?e8 (a8) and e6 (a6)?e0 (a0) are reserved for future use and must all be pro- grammed to ?0.? a13 is not used in x16 configuration. ck ck# command dq dqs, dqs# active n t0 t1 t2 don?t care transitionin g data nop nop t3 t4 t5 nop write n t6 nop d in n + 3 d in n + 2 d in n + 1 wl = al + cl - 1 = 4 t7 nop d in n t rcd (min) nop al = 2 cl - 1 = 2 a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 exten d e d mo d e re g ister (ex) a dd ress bus 976543 82 1 0 a10 a12 a11 ba0 ba1 1 0 11 1 2 1 3 0 1 1 4 1 5 a13 0 1 0 1 mode register definition mo d e re g ister (mr) exten d e d mo d e re g ister (emr) exten d e d mo d e re g ister (emr2) exten d e d mo d e re g ister (emr3) m 1 5 0 0 1 1 m 1 4 emr2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 high temperature self refresh rate enable c ommer c ial temperature d efault in d ustrial temperature option; use if t c ex c ee d s 85 c e7 0 1
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 28 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram extended mode register 3 extended mode register 3 the extended mode register 3 (emr3) controls functions beyond those controlled by the mode register. currently all bits in emr3 are reserved, as shown in figure 14 on page 28. the emr3 is programmed via the lm command and will retain the stored information until it is programmed again or the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. emr3 must be loaded when all banks are id le and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requiremen ts could result in unspecified operation. figure 14: extended mode register 3 (emr3) definition notes: 1. e13 (a13)?e0 (a0) are reserved for future use and must all be programmed to ?0.? a13 is not used in x16 configuration. a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 exten d e d mo d e re g ister (ex) a dd ress bus 976543 82 1 0 a10 a12 a11 ba0 ba1 1 0 11 1 2 1 3 1 4 1 5 a13 0 1 0 1 mode register definition mo d e re g ister (mr) exten d e d mo d e re g ister (emr) exten d e d mo d e re g ister (emr2) exten d e d mo d e re g ister (emr3) m 1 5 0 0 1 1 m 1 4 emr3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 29 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram command truth tables command truth tables the following tables provide a quick reference of ddr2 sdram available commands, including cke power-down modes, and bank-to-bank commands. notes: 1. all ddr2 sdram commands are defined by st ates of cs#, ras#, cas#, we#, and cke at the rising edge of the clock. 2. bank addresses (ba) ba0?ba1 determine which bank is to be operated upon. ba during a lm command selects which mo de register is programmed. 3. burst reads or writes at bl = 4 cannot be terminated or interrupted. see figure 21 on page 40 and figure 35 on page 53 fo r other restrictions and details. 4. the power-down mode does not perform any refresh operations. the duration of power- down is limited by the refresh requiremen ts outlined in the ac parametric section. 5. the state of odt does not affect the states de scribed in this table. the odt function is not available during self re fresh. see ?odt timing? on page 74 for details. 6. ?x? means ?h or l? (but a defined logic level). 7. self refresh exit is asynchronous. table 5: truth table ? ddr2 commands notes: 1, 5, an d 6 apply to all function cke cs# ras# cas# we# ba1 ba0 a13, a12, a11 a10 a9?a0 notes previous cycle current cycle load mode h h l l l l ba op code 2 refresh hhlllhxxxx self refresh entry hllllhxxxx self refresh exit lh hx xx xxxx 7 lhhh single bank prechar g e hhllhlbaxlx2 all banks prechar g e hhllhlxxhx bank activate h h l l h h ba row address write hhlhllba column address l column address 2, 3 write with auto precharge hhlhllba column address h column address 2, 3 read hhlhlhba column address l column address 2, 3 read with auto precharge hhlhlhba column address h column address 2, 3 no operation hxlhhhxxxx device deselect hxhxxxxxxx power-down entry hl hx xx xxxx 4 lhhh power-down exit lh hx xx xxxx 4 lhhh
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 30 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram command truth tables notes: 1. this table applies when cke n - 1 was hi g h and cke n is hi g h and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where note d (the current state is for a specific bank and the commands shown are those allo wed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issu ed to the same bank. issue deselect or nop commands, or allowable commands to the other bank, on any clock edge occurring during these states. allowable commands to the ot her bank are determined by its current state and this table, an d according to table 7 on page 32. table 6: truth table ? current state bank n - command to bank n notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle llhh active (select and activate row) lllh refresh 7 llll load mode 7 row active lhlh read (select column and start read burst) 9 lhl l write (select column an d start write burst) 9 llhl prechar g e (deactivate row in bank or banks) 8 read (auto- precharge disabled lhlh read (select column and start new read burst) 9 lhl l write (select column and start write burst) 9, 10 llhl prechar g e (start prechar g e) 8 write (auto- precharge disabled) lhlh read (select column and start read burst) 9 lhl l write (select column and start new write burst) 9 llhl prechar g e (start prechar g e) 8 idle: the bank has been precharged, t rp has been met, and any read burst is complete. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated. precharging: starts with registration of a prechar g e command and ends when t rp is met. once t rp is met, the bank will be in the idle state. read with auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. write with auto precharge enabled: starts with registration of a wri te command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 31 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram command truth tables 5. the following states must not be interrupt ed by any executable command (deselect or nop commands must be applied on each pos itive clock edge during these states): 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; requires that all bank s are idle and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. reads or writes listed in the command/action column includ e reads or writes with auto precharge enabled and reads or writ es with auto precharge disabled. 10. a write command may be applied after the comple tion of the read burst. refreshing: starts with registration of a refresh command and ends when t rfc is met. once t rfc is met, the ddr2 sdram will be in the all banks idle state. accessing mode register: starts with registration of th e lm command and ends when t mrd has been met. once t mrd is met, the ddr2 sdram will be in the all banks idle state. precharging all: starts with registration of a prechar g e all command and ends when t rp is met. once t rp is met, all banks will be in the idle state.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 32 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram command truth tables notes: 1. this table applies when cke n - 1 was hi g h and cke n is hi g h and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where no ted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given comma nd is allowable). exceptions are covered in the notes below. 3. current state definitions: table 7: truth table ? current state bank n - command to bank m notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continu e previous operation) lhhh no operation (nop/conti nue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl prechar g e read (auto precharge disabled llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl prechar g e write (auto precharge disabled.) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8 lhl l write (select column and start new write burst) 7 llhl prechar g e read (with auto- precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 3 lhl l write (select column and start write burst) 7, 9, 3 llhl prechar g e write (with auto- precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 3 lhl l write (select column and start new write burst) 7, 3 llhl prechar g e idle: the bank has been precharged, t rp has been met, and any read burst is complete. row active: a row in the ba nk has been activated and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated with auto precharge disabled, and has not yet terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 33 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram command truth tables the minimum delay from a read or wr ite command with auto precharge enabled to a command to a differen t bank is summarized in table 8: 4. refresh and lm commands may only be issued when all banks are idle. 5. not used. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writ es with auto pr echarge disabled. 8. requires appropriate dm. 9. a write command may be applied afte r the completion of the read burst. 10. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. read with auto precharge enabled/ write with auto precharge enabled: the read with auto prec harge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was execut ed with auto precharge disabled and then followed with the earliest possible prechar g e command that still accesses all of the data in the burst. for write with au to precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access peri od starts with registration of the command and ends where the precharge period (or t rp) begins. this device supports concurrent auto precharge su ch that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. in either case, all other related limitations ap ply (contention between re ad data and write data must be avoided). table 8: minimum delay with auto precharge enabled from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read with auto precharge (cl - 1) + (bl / 2) + t wtr t ck write or write with auto precharge (bl / 2) t ck prechar g e or active 1 t ck read with auto precharge read or read with auto precharge (bl / 2) t ck write or write with auto precharge (bl / 2) + 2 t ck prechar g e or active 1 t ck
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 34 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram deselect, nop, and lm commands deselect, nop, and lm commands deselect the deselect function (cs# high) prevents new commands from being executed by the ddr2 sdram. the ddr2 sdram is effectively deselected. operations already in progress are not affected. deselect is also referred to as command inhibit. no operation (nop) the no operation (nop) command is used to instruct the select ed ddr2 sdram to perform a nop (cs# is low; ras#, cas#, and we are high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode (lm) the mode registers are loaded via inputs ba 1?ba0 and a13?a0 for x4 and x8, and a12?a0 for x16 configurations. ba1?ba0 determine which mode register will be programmed. see ?mode register (mr)? on page 19. the lm command can only be issued when all banks are idle, and a subsequent execut able command cannot be issued until t mrd is met. bank/row activation active command the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba1?ba0 inputs selects the bank, and the address provided on inputs (a13?a0 for x4 and x8, an d a12?a0 for x16) selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. active operation before any read or write commands can be issued to a bank within the ddr2 sdram, a row in that bank must be opened (activated), even when additive latency is used. this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 15 on page 35. after a row is opened with an active command, a read or write command may be issued to that row subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. the same procedure is used to convert other specification limits from time units to clock cycles. for example, a t rcd (min) specification of 20ns with a 266 mhz clock ( t ck = 3.75ns) results in 5.3 clocks, rounded up to 6. this is reflected in figure 17 on page 37, which covers any case where 5 < t rcd (min) / t ck 6. figure 17 also shows the case for t rrd where 2 < t rrd (min) / t ck 3. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been clos ed (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 35 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram bank/row activation a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. figure 15: active command ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to t rcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. don ? t c are c k c k# cs # ra s # c a s # we# c ke row bank addre ss bank addre ss
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 36 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads reads read command the read command is used to initiate a burst read access to an active row. the value on the ba1?ba0 inputs selects the bank, an d the address provided on inputs a0? i (where i = a9 for x16, a9 for x8, or a9, a11 for x4) sele cts the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read operation read bursts are initiated with a read comm and, as shown in figure 16 on page 37. the starting column and bank addresses are pr ovided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is automatica lly precharged at the completion of the burst. if auto precharge is disabled, the row wi ll be left open after the completion of the burst. during read bursts, the valid data-out elem ent from the starting column address will be available read latency (rl) clocks later. rl is defined as the sum of al and cl; rl = al + cl. the value for al and cl are programmable via the mr and emr commands, respectively. each subsequent data -out element will be valid nominally at the next positive or negative clock edge (i .e., at the next crossing of ck and ck#). figure 18 on page 38 shows examples of rl based on different al and cl settings. dqs/dqs# is driven by the ddr2 sdram alon g with output data. the initial low state on dqs and high state on dqs# is known as the read preamble ( t rpre). the low state on dqs and high state on dqs# coincident wi th the last data-out element is known as the read postamble ( t rpst). upon completion of a burst, assuming no ot her commands have been initiated, the dq will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window are depicted in figure 27 on page 46 and figure 28 on page 47. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is shown in figure 29 on page 48. data from any read burst may be concatenated with data from a subsequent read command to provide a continuous flow of data. the first data element from the new burst follows the last element of a complete d burst. the new read command should be issued x cycles after the first read command, where x equals bl / 2 cycles. this is shown in figure 19 on page 39.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 37 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 16: read command figure 17: example: meeting t rrd (min) and t rcd (min) don ? t c are c k c k# cs # ra s # c a s # we# c ke c ol bank addre ss bank addre ss auto pre c harge enable di s able a10 m and don ? t c are t1 t0 t2 t3 t4 t5 t 6 t7 t rrd row row c ol bank x bank y bank y nop a c t nop nop a c t nop nop rd/wr t r c d 0 , ba1 c k# d re ss c k t8 t9 nop nop
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 38 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 18: read latency notes: 1. do n = data-out from column n . 2. bl = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. read nop nop nop nop nop bank a , col n ck ck# command address dq dqs, dqs# do n do n t0 t1 t2 t3 t4n t5n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 3 (al = 0, cl = 3) dq dqs, dqs# do n t0 t1 t2 t3 t3n t4n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 4 (al = 0, cl = 4) dq dqs, dqs# t0 t1 t2 t3 t3n t4n t4 t5 al = 1 cl = 3 rl = 4 (al = 1 + cl = 3) don?t care transitionin g data
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 39 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 19: consecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read co mmands are issued to same device. nonconsecutive read data is illustrated in figure 20 on page 40. full-speed random read accesses within a page (or pages) can be performed. ddr2 sdram supports the use of concurrent auto precharge timing , shown in table 9 on page 41. ddr2 sdram does not allow interrupting or truncating of any read burst using bl = 4 operations. once the bl = 4 read command is registered, it must be allowed to complete the entire read burst. however, a read (with auto precharge disabled) using bl = 8 operation may be interrupted and truncated only by another read burst as long as the interruption occurs on a 4-bit boundary due to the 4 n prefetch architecture of ddr2 sdram. read burst bl = 8 operations may not be interrupted or truncated with any command except another read command, as shown in figure 21 on page 40. ck ck# command read nop read nop nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b rl = 3 ck ck# command address dq dqs, dqs# rl = 4 dq dqs, dqs# do n do b do n do b t0 t1 t2 t3 t3n t4n t4 t5 t6 t5n t6n t0 t1 t2 t3 t2n nop t3n t4n t4 t5 t6 t5n t6n don?t care transitionin g data t ccd t ccd
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 40 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 20: nonconsecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies when read co mmands are issued to differen t devices or nonconsecutive reads. figure 21: read interrupted by read notes: 1. bl = 8 required; auto precha rge must be disabl ed (a10 = low). 2. read command can be issued to any valid bank and row ad dress (read command at t0 and t2 can be either same ba nk or different bank). 3. interrupting read command mu st be issued exactly 2 x t ck from previous read. 4. auto precharge can be either enabled (a10 = hi g h) or disabled (a10 = low) by the inter- rupting read command. 5. nop or command inhibit co mmands are valid. prechar g e command cannot be issued to banks used for reads at t0 and t2. 6. example shown uses al = 0; cl = 3, bl = 8, shown with nominal t ac, t dqsck, and t dqsq. ck ck# command read nop nop nop nop nop nop nop address bank, col n read bank, col b command address cl = 3 ck ck# command address dq dqs, dqs# cl = 4 dq dqs, dqs# do n t0 t1 t2 t3 t3n t4 t5 t7 t8 t6 t4n t6n t7n nop nop nop nop t5 t7 t8 t5n t6 t4n t7n read nop nop nop bank, col n read bank, col b t0 t1 t2 t3 t4 do b do n do b don?t care transitionin g data ck ck# command dq dqs, dqs# cl = 3 (al = 0) read 1 t0 t1 t2 don?t care transitionin g data nop 5 nop 5 d out t3 t4 t5 valid valid t6 valid read 3 valid valid valid t7 t8 t9 cl = 3 (al = 0) t ccd address a10 valid 4 valid 2 valid 2 d out d out d out d out d out d out d out d out d out d out d out
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 41 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads data from any read burst must be completed before a subsequent write burst is allowed. an example of a read burst followed by a write burst is shown in figure 24 on page 43. the t dqss (min) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in figure 31 on page 51.) a read burst may be followed by a precha rge command to the same bank, provided that auto precharge was not activated. the minimum read-to-precharge command spacing to the same bank is al + bl/2 cloc ks and must also satisfy a minimum analog time from the rising clock edge that init iates the last 4-bit prefetch of a read-to- precharge command. this read-t o-precharge time is called t rtp. for bl = 4 this is the time from the actual read (al after the read command) to precharge command. for bl = 8 this is the time fr om al + 2ck after the read-to-precharge command. following the precharge command , a subsequent command to the same bank cannot be issued until t rp is met. note: part of the row precharge time is hidden du ring the access of the last data elements. examples of read-to-precharge are shown in figure 22 on page 42 for bl = 4 and figure 23 on page 42 for bl = 8. the delay from read-to-precharge command to the same bank is al + bl/2 + max ( t rtp/ t ck or 2ck) - 2ck. if a10 is high when a read command is issued, the read with auto precharge function is engaged. the ddr2 sdram starts an auto precharge operation on the rising edge, which is al + (bl/2) cycles later than the read with auto precharge command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, the start point of auto precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of the auto precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp, t rp starts at the point where the internal precha rge happens (not at the next rising clock edge after this event). for bl = 4, the mini mum time from read with auto precharge to the next activate command becomes al + ( t rtp + t rp)*, shown in figure 22 on page 42; for bl = 8, the time from read with auto precharge to the next activate command is al + 2 clocks + ( t rtp + t rp)*, shown in figure 23 on page 42. the * indicates each parameter term is divided by t ck and rounded up to the next integer. in any event, internal precharge does not start earlier than two clocks after the last 4-bit prefetch. table 9: read using concurrent auto precharge from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units read with auto precharge read or read with auto precharge bl/2 t ck write or write with au to precharge (bl/2) + 2 t ck prechar g e or active 1 t ck
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 42 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 22: read-to-precharge ? bl = 4 notes: 1. rl = 4 (al = 1, cl = 3); bl = 4. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. figure 23: read-to-precharge ? bl = 8 notes: 1. rl = 4 (al = 1, cl = 3); bl = 8. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. ck ck# command dq dqs, dqs# cl = 3 read t0 t1 t2 don?t care transitionin g data nop prech g d out t3 t4 t5 t6 active t7 address a10 al = 1 nop bank a t rtp (min) bank a t ras (min) bank a t rp (min) nop nop al + bl/2 + max( t rtp/ t ck or 2ck) - 2ck nop t rc (min) 4-bit prefetch valid valid d out d out d out ck ck# command dq dqs, dqs# cl = 3 read t0 t1 t2 don?t care transitionin g data nop d out t3 t4 t5 t6 t7 t8 address a10 al = 1 nop bank a t rc (min) t rtp (min) nop nop first 4-bit prefetch second 4-bit prefetch t rp (min) prech g bank a bank a nop nop active t ras (min) valid valid al + bl/2 + max( t rtp/ t ck or 2ck) -2ck d out d out d out d out d out d out d out
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 43 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 24: read-to-write notes: 1. bl = 4; cl = 3; al = 2. 2. shown with nominal t ac, t dqsck, and t dqsq. c k c k# c ommand dq dq s , dq s # al = 2 a c tive n t0 t1 t2 don ? t c are tran s itioning data nop nop d out n t3 t4 t5 nop write n t 6 nop wl = rl - 1 = 4 t7 t8 nop nop nop t9 t10 t11 nop nop c l = 3 rl = 5 t r c d = 3 read n d out n + 1 d out n + 2 d out n + 3 d in n d in n + 1 d in n + 2 d in n + 3 nop nop nop write
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 44 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 25: bank read ? without auto precharge notes: 1. do n = data-out from column n ; subsequent elements are applied in the programmed order. 2. bl = 4 and al = 0 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is hi g h at t5. 5. pre = prechar g e, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. the prechar g e command can only be applied at t6 if t ras (min) is met. 8. read-to-prechar g e = al + bl/2 + ( t rtp - 2 clocks). 9. i/0 balls, when entering or exiting hi g h-z are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras 7 t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t 8 n t 6 t7 t 8 dq 1 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 1 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (min) do n nop 6 nop 6 command 5 act ra col n pre 7 bank x ra ra bank x bank x 4 9 9 99 act bank x nop 6 nop 6 nop 6 nop 6 t hz (min) one bank all banks don?t care transitionin g data read 2 address 3 t rtp 8
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 45 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 26: bank read ? with auto precharge notes: 1. do n = data-out from column n ; subsequent elements are applied in the programmed order. 2. bl = 4, rl = 4 (al = 1, cl = 3) in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. the ddr2 sdram internally dela ys auto precha rge until both t ras (min) and t rtp (min) have been satisfied. 7. i/0 balls, when entering or exiting hi g h-z are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. 4-bit prefetch ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 1 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 1 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (max) do n nop 5 nop 5 command 5 act ra col n bank x ra ra bank x act bank x nop 5 nop 5 nop 5 nop 5 nop 5 t hz (min) don?t care transitionin g data read 2,6 address al = 1 t rtp internal precharge 3 7 7 77
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 46 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 27: x4, x8 data output timing ? t dqsq, t qh, and data valid window notes: 1. dq transitioning af ter dqs transition define t dqsq window. dqs transitions at t2 and at t2n are ?early dqs,? at t3 are ?nomin al dqs,? and at t3n are ?late dqs.? 2. dq0, dq1, dq2, dq3 fo r x4 or dq0?dq7 for x8. 3. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 6. the data valid window is derived for each dqs transition and is defined as t qh - t dqsq. dq (last data valid) dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 dqs# dqs 1 dq (last data valid) dq (first data no longer valid) dq (first data no longer valid) all dqs and dqs, collectively 6 earliest signal transition latest signal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window data valid window data valid window
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 47 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 28: x16 data output timing ? t dqsq, t qh, and data valid window notes: 1. dq transitioning after dqs transitions define the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq 6, or dq7. 3. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 6. the data valid window is derive d for each dqs transition and is t qh - t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. dq (last d ata vali d ) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ld s q# ldq s 1 dq (last d ata vali d ) 2 dq (first d ata no lon g er vali d ) 2 dq (first d ata no lon g er vali d ) 2 dq0?dq7 an d ldq s , c olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n c k c k# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dq s q 3 t dq s q 3 t dq s q 3 t dq s q 3 data vali d win d ow data vali d win d ow dq (last d ata vali d ) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udq s # udq s 1 dq (last d ata vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq8?dq15 an d udq s , c olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dq s q 3 t dq s q 3 t dq s q 3 t dq s q 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow upper byte lower byte data vali d win d ow
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 48 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reads figure 29: data output timing ? t ac and t dqsck notes: 1. t dqsck is the dqs output window relative to ck and is the ?long-term? component of dqs skew. 2. dq transitioning after dqs transitions define t dqsq window. 3. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 4. t ac is the dq output window relative to ck and is the ?long term? component of dq skew. 5. t lz (min) and t ac (min) are the first valid signal transitions. 6. t hz (max) and t ac (max) are the latest va lid signal transitions. 7. read command with cl = 3, al = 0 issued at t0. 8. i/o balls, when entering or exiting hi g h-z, are not referenced to a specific voltage level, but to when the device begins to driv e or no longer drives, respectively. ck ck# dqs#/dqs, or ldqs#/ldqs / udq#/udqs 2 t0 7 t1 t2 t3 t3n t4 t4n t5 t5n t6 t6n t7 t rpst t lz (min) t dqsck 1 (min) t dqsck 1 (max) t hz (max) t rpre dq (last data valid) dq (first data valid) all dqs collectively 3 t ac 4 (min) t ac 4 (max) t lz (min) t hz (max) t3 t3 t3n t4n t5n t6n t3n t3n t4n t4n t5n t5n t6n t6n t4 t5 t5 t6 t6 t3 t4 t5 t6 t4
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 49 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes writes write command the write command is used to initiate a burst write access to an active row. the value on the ba1?ba0 inputs selects the bank, and the address provided on inputs a0? i (where i = a9 for x8 and x16; or a9, a11 for x4) sele cts the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be prec harged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. figure 30: write command note: ca = column address; ba = bank address; en ap = enable auto precharge; and dis ap = dis- able auto precharge. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory ; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location (figure 40 on page 58). write operation write bursts are initiated with a writ e command, as shown in figure 30. ddr2 sdram uses wl equal to rl minus one clock cycle [wl = rl - 1ck = al + (cl - 1ck)]. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. cs # we# c a s # ra s # c ke c a a10 bank addre ss high en ap di s ap ba c k c k# don ? t c are addre ss
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 50 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first rising dqs edge is wl t dqss. subsequent dqs positive rising edges are timed, relative to the associated clock edge, as t dqss. t dqss is specified with a relatively wide range (25 percent of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases ( t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 31 on page 51 shows the no minal case and the extremes of t dqss for bl = 4. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. data for any write burst may be concatenat ed with a subsequent write command to provide continuous flow of input data. the first data element from the new burst is applied after the last element of a comple ted burst. the new write command should be issued x cycles after the first write command, where x equals bl/2. figure 32 on page 52 shows concatenated burs ts of bl = 4. an example of nonconsecu- tive writes is shown in figure 33 on page 52. full-speed random write accesses within a page or pages can be performed as shown in figure 34 on page 53. ddr2 sdram supports concurrent auto precharge options, as shown in table 10. ddr2 sdram does not allow interrupting or truncating any write burst using bl = 4 operation. once the bl = 4 write command is registered, it must be allowed to complete the entire write burst cycle. howe ver, a write bl = 8 operation (with auto precharge disabled) might be interrupted and truncated only by another write burst as long as the interruption occurs on a 4-bit boundary, due to the 4 n prefetch architec- ture of ddr2 sdram. write burst bl = 8 operations may not be interrupted or trun- cated with any command except another wr ite command, as shown in figure 35 on page 53. data for any write burst may be followed by a subsequent read command. to follow a write, t wtr should be met, as shown in figure 36 on page 54. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. data for any write burst may be followed by a subsequent precharge command. t wr must be met, as shown in figure 37 on page 55. t wr starts at the end of the data burst, regardless of the data mask condition. table 10: write using concurrent auto precharge from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read with auto precharge (cl - 1) + (bl/2) + t wtr t ck write or write with auto precharge (bl/2) t ck prechar g e or active 1 t ck
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 51 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 31: write burst notes: 1. di b = data-in for column b . 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 4. a10 is low with the write comm and (auto precharge is disabled). 5. subsequent rising dq s signals must align to the clock within t dqss. dqs, dqs# t dq ss (max) t dq ss (nom) t dq ss (min) wl t dqss dm dq ck ck# command write nop nop address bank a , col b nop nop t0 t1 t2 t3 t2n t4 t3n dqs, dqs# wl + t dqss 5 5 5 dm dq dqs, dqs# wl - t dqss dm dq di b di b di b don?t care transitionin g data t dqss t dqss
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 52 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 32: consecutive write-to-write notes: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in ar e applied in the programmed order following di b . 3. three subsequent elements of data-in are applied in the progra mmed order following di n . 4. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 5. each write command may be to any bank. 6. subsequent rising dq s signals must align to the clock within t dqss. figure 33: nonconsecutive write-to-write notes: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. three subsequent elements of data-in are applied in the progra mmed order following di n . 4. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 5. each write command may be to any bank. 6. subsequent rising dq s signals must align to the clock within t dqss. ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b don?t care transitionin g data wl t dqss t dq ss (nom) wl = 2 t ccd wl = 2 6 6 6 ck ck# command write nop nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t5n t6 t6n dq dqs, dqs# dm di n di b t dqss (nom) wl t dqss don?t care transitionin g data wl = 2 wl = 2 6 66
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 53 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 34: random write cycles notes: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. three subsequent elements of data-in are applied in the progra mmed order following di n . 4. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 5. each write command may be to any bank. 6. subsequent rising dq s signals must align to the clock within t dqss. figure 35: write interrupted by write notes: 1. bl = 8 required and auto precharge must be disabled (a10 = low). 2. write command can be issued to any vali d bank and row address (write command at t0 and t2 can be either same bank or different bank). 3. interrupting write command must be issued exactly 2 x t ck from previous write. 4. auto precharge can be either enabled (a10 = hi g h) or disabled (a10 = low) by the inter- rupting write command. 5. nop or command inhibit co mmands are valid. prechar g e command cannot be issued to banks used for writes at t0 and t2. 6. earliest write-to-prechar g e timing for write at t0 is wl + bl/2 + t wr where t wr starts with t7 and not t5 (since bl = 8 from mr and not the truncated length). 7. example shown uses al = 0; cl = 4, bl = 8. 8. subsequent rising dq s signals must align to the clock within t dqss. ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b don?t care transitionin g data wl t dqss t dq ss (nom) wl = 2 t ccd wl = 2 6 6 6 ck ck# command dq dqs, dqs# wl = 3 write 1 a t0 t1 t2 don?t care transitionin g data d in a t3 t4 t5 t6 write 3 b d in b t7 t8 t9 wl = 3 2 clock requirement address a10 valid 4 valid 2 valid 2 valid 6 valid 6 valid 6 nop 5 nop 5 nop 5 nop 5 nop 5 8 8888 d in a + 1 d in a + 3 d in a + 2 d in b + 1 d in b + 2 d in b + 3 d in b + 4 d in b + 5 d in b + 6 d in b + 7
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 54 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 36: write-to-read notes: 1. di b = data-in for column b ; d out n = data-out from column n . 2. bl = 4, al = 0, cl = 3; thus, wl = 2. 3. one subsequent element of data-in is ap plied in the programme d order following di b . 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. a10 is low with the write comm and (auto precharge is disabled). 6. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. 7. t wtr is required for any read following a write to the same device, but it is not required between module ranks. 8. subsequent rising dq s signals must align to the clock within t dqss. t dq ss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t9n t3n t6 t7 t8 t9 t wtr 7 cl = 3 cl = 3 cl = 3 dq dqs, dqs# dm di b t dq ss (min) dq dqs, dqs# dm di b t dq ss (max) dq dqs, dqs# dm di b do ut do ut don?t care transitionin g data wl t dqss wl - t dqss wl + t dqss nop do ut 8 8 8
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 55 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 37: write-to-precharge notes: 1. di b = data-in for column b . 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. bl = 4, cl = 3, al = 0; thus, wl = 2. 4. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 5. the prechar g e and write commands are to the same bank. however, the prechar g e and write commands may be to different banks, in which case t wr is not required and the prechar g e command could be applied earlier. 6. a10 is low with the write comm and (auto precharge is disabled). 7. pre = prechar g e command. 8. subsequent rising dq s signals must align to the clock within t dqss. t dq ss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t3n t6 t7 t wr t rp dq dqs# dqs dm di b t dq ss (min) dq dqs# dqs dm di b t dq ss (max) dq dqs# dqs dm di b don?t care transitionin g data wl + t dqss wl - t dqss wl + t dqss pre 7 8 8 8
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 56 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 38: bank write ? without auto precharge notes: 1. di n = data-in from column n ; subsequent elements are applied in the programmed order. 2. bl = 4, al = 0, and wl = 2 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is hi g h at t9. 5. pre = prechar g e, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. 9. subsequent rising dq s signals must align to the clock within t dqss. ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rp t wr t0 t1 t2 t3 t5 t6 t6n t7 t8 t9 t5n nop 6 nop 6 command 5 3 9 act ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dm di n don?t care transitionin g data wl t dqss (nom) t wpre dqs, dqs# address nop 6 wl = 2 t4
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 57 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 39: bank write ? with auto precharge notes: 1. di n = data-in from column n ; subsequent elements are applied in the programmed order. 2. bl = 4, al = 0, and wl = 2 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 7. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. 8. wr is programmed via mr[11, 10, 9] and is calculated by dividing t wr (in nanoseconds) by t ck and rounding up to the next integer value. 9. subsequent rising dq s signals must align to the clock within t dqss. ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rp wr 8 t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t6n nop 5 nop 5 command 4 3 act ra col n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dqsl t dqsh t wpst dq 1 dm wl t dqss (nom) don?t care transitionin g data t wpre dqs,dqs# address t9 nop 5 wl = 2 di n 9
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 58 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 40: write ? dm operation notes: 1. di n = data-in from column n ; subsequent elements are applied in the programmed order. 2. burst length = 4, al = 1, and wl = 2 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is hi g h at t11. 5. pre = prechar g e, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t6 or t7. 8. t dss is applicable during t dqss (max) and is referenced from ck t7 or t8. 9. t wr starts at the end of the data burst regardless of the data mask condition. 10. subsequent rising dq s signals must align to the clock within t dqss. ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rp a t wr 9 t0 t1 t2 t3 t4 t5 t7n t6 t7 t8 t6n nop 6 nop 6 command 5 3 act ra col n write 2 nop 6 one bank all banks bank x bank x nop 6 nop 6 nop 6 nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dm don?t care transitionin g data wl t dqss (nom) t wpre pre dqs, dqs# address t9 t10 t11 al = 1 wl = 2 di n 10
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 59 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram writes figure 41: data input timing notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. write command issued at t0. 4. for x16, ldqs controls the lower byte and udqs controls the upper byte. 5. write command with wl = 2 (cl = 3, al = 0) issued at t0. 6. subsequent rising dq s signals must align to the clock within t dqss. dqs dqs# wl - t dqss (nom) t dqsh t wpst t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2 dm dq ck ck# t1 t0 t1n t2 t2n t3 t4 t3n di don?t care transitionin g data t wpre 6
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 60 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram precharge precharge precharge command the precharge command, illustrated in figure 42 on page 60, is used to deactivate the open row in a particular bank or the open ro w in all banks. the bank(s) will be available for a subsequent row activation a specified time ( t rp) after the precharge command is issued, except in the case of concurre nt auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a prec harge command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank. precharge operation input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba1?ba0 select the bank. otherwise ba1?ba0 are treated as ?don?t care.? when all banks are to be precharged, inputs ba1?ba0 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. t rpa timing applies when the precharge (all) command is issued, regardle ss of the number of banks already open or closed. if a single-bank precharge command is issued, t rp timing applies. figure 42: precharge command note: ba = bank address (if a10 is low; otherwise ?don?t care?). cs# we# cas# ras# cke a10 ba0, ba1 hi g h all banks one bank ba address ck ck# don?t care
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 61 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram self refresh self refresh self refresh command the self refresh command can be used to re tain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocki ng. all power supply inputs (including v ref ) must be maintained at valid levels upon entry/exit and during self refresh opera- tion. the self refresh command is initiated like a refresh command except cke is low. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). the differential clock should remain stable and meet t cke specifications at least 1 x t ck after entering self refresh mode. all command and address input signals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, the differ- ential clock must be stable and meet t ck specifications at least 1 x t ck prior to cke going back high. once cke is high ( t cke [min] has been satisfied with four clock registrations), the ddr2 sdram must have nop or deselect commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nop or deselect commands for 200 clock cycles before applying any other command.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 62 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram self refresh figure 43: self refresh notes: 1. clock must be stable and meeting t ck specifications at least 1 x t ck after entering self refresh mode and at least 1 x t ck prior to exiting self refresh mode. 2. device must be in the all banks idle sta te prior to entering self refresh mode. 3. t xsnr is required before any non-read command can be applied. 4. t xsrd (200 cycles of ck) is required before a read command can be applied at state td0. 5. ref = refresh command. 6. self refresh exit is asynchronous; however, t xsnr and t xsrd timing starts at the first rising clock edge where cke hi g h satisfies t isxr. 7. nop or deselect commands are required prior to exiting self refresh until state tc0, which allows any non-read command. 8. odt must be disabled and r tt off ( t aofd and t aofpd have been satisfied) prior to entering self refresh at state t1. 9. once self refresh has been entered, t cke (min) must be satisfied pr ior to exiting self refresh. 10. cke must stay hi g h until t xsrd is met; however, if self refresh is being re-entered, cke may go back low after t xsnr is satisfied. 11. once exiting self refresh, odt must remain low until t xsrd is satisfied. c k 1 c k# c ommand 5 nop ref addre ss c ke 1 valid dq dm dq s #, dq s nop 7 t rp 2 t c h t c l t c k 1 t c k 1 t x s nr 3, 6 , 11 t i s xr 6 enter self refresh mo d e (syn c hronous) exit self refresh mo d e (asyn c hronous) t0 t1 ta2 ta1 don ? t c are ta0 t c 0 t b 0 t x s rd 4, 6 valid 3 nop 7 t c ke (min) 9 t2 odt 8 t aofd / t aofpd 8 t d 0 valid 4 valid 3 in d i c ates a b reak in time s c ale t ih t ih t c ke 10
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 63 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram refresh refresh refresh command refresh is used during normal operatio n of the ddr2 sdram and is analogous to cas#-before-ras# (cbr) refresh. this comm and is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an refresh command. the 512mb ddr2 sdram requires refresh cycl es at an average interval of 7.8125s (max). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted (to defer issuing refresh commands) to any given ddr2 sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 7.8125s (70.3s; 3.9s for high- temperature operation). the refresh period begins when the refresh command is registered and ends t rfc (min) later. figure 44: refresh mode notes: 1. pre = prechar g e, act = active, ar = refresh, ra = row address, ba = bank address. 2. nop commands are shown for ease of illustra tion; other valid commands may be possible at these times. cke must be active during clock positive transitions. 3. ?don?t care? if a10 is hi g h at this point; a10 must be hi g h if more than one bank is active (i.e., must precharge all active banks). 4. dm, dq, and dqs signals are all ?don ?t care?/high-z for operations shown. 5. the second refresh is not required and is on ly shown as an example of two back-to-back refresh commands. ck ck# command 1 nop 2 nop 2 nop 2 pre cke ra address a10 1 bank 1 bank(s) 3 ba ref nop 2 ref 5 nop 2 act nop 2 one bank all banks t ck t ch t cl ra dq 4 dm 4 dqs, dqs# 4 t rfc 5 t rp t rfc(min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 don?t care indicates a break in time scale
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 64 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode power-down mode ddr2 sdrams support multiple power-do wn modes that allow significant power savings over normal operating modes. cke is used to enter and exit different power- down modes. power-down entry and exit timings are shown in figure 45 on page 65. detailed power-down entry conditions are shown in figures 46 through 53. the cke truth table, table 11, is shown on page 66. ddr2 sdrams require cke to be registered high (active) at all times that an access is in progress?from the issuing of a read or write command until completion of the burst. thus, a clock suspend is not supported. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble and t wr or t wtr are satisfied, as shown in figures 48 and 49 on page 68. the number of clock cycles required to meet t wtr is either two or t wtr/ t ck, whichever is greater. power-down mode (see figure 45 on page 65 ) is entered when cke is registered low coincident with a nop or deselect command . cke is not allowed to go low during a mode register or extended mode register command time, or while a read or write operation is in progress. if power-down occu rs when all banks are idle, this mode is referred to as precharge power-down. if power-down occurs when there is a row active in any bank, this mode is referred to as acti ve power-down. entering power-down deacti- vates the input and output buffers, excluding ck, ck#, odt, and cke. for maximum power savings, the dll is frozen during precharge power-down. exiting active power- down requires the device to be at the same voltage and frequency as when it entered power-down. exiting precharge power-down requires the device to be at the same voltage as when it entered power-down; however, the clock frequency is allowed to change. see ?precharge power-down clock frequency change? on page 71. the maximum duration for either active or precharge power-down is limited by the refresh requirements of the device t rfc (max). the minimum duration for power-down entry and exit is limited by the t cke (min) parameter. while in power-down mode, cke low, a stable clock signal, and stable power supply signals must be maintained at the inputs of the ddr2 sdram, while all other input signals are ?don?t care? except odt. detailed odt timing diagrams for different power-down modes are shown in figures 56 through 63. the power-down state is synchronously exited when cke is registered high (in conjunction with an nop or deselect command), as shown in figure 45 on page 65.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 65 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode figure 45: power-down notes: 1. if this command is a prechar g e (or if the device is already in the idle state), then the power-down mode shown is precharge power-down . if this command is an active (or if at least one row is already active ), then the power-down mode shown is active power-down. 2. no column accesses ar e allowed to be in progress at the ti me power-down is entered. if the dll was not in a locked state when cke went low, the dll must be reset after exiting power-down mode for proper read operation. 3. t cke (min) of three clocks means cke must be re gistered on three consecutive positive clock edges. cke must remain at the va lid input level the en tire time it takes to achieve the three clocks of registration. thus, after any cke tr ansition, cke may not tr ansition from its valid level during the time period of t is + 2 x t ck + t ih. cke must not transition during its t is and t ih window. 4. t xp timing is used for exit precharge power-down and active power-down to any non-read command. 5. t xard timing is used for exit active power-do wn to read command if fast exit is selected via mr (bit 12 = 0). 6. t xards timing is used for exit active power-do wn to read command if slow exit is selected via mr (bit 12 = 1). ck ck# command nop nop nop address cke dq dm dqs, dqs# valid t ck t ch t cl enter power-down mode 2 exit power-down mode don?t care t cke (min) 3 t cke (min) 3 valid valid 1 valid t xp 4 , t xard 5 t xards 6 valid valid t is t ih t ih t1 t2 t3 t4 t5 t6 t7 t8
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 66 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode notes: 1. cke ( n ) is the logic state of cke at clock edge n ; cke ( n -1) was the state of cke at the previ- ous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n . 3. command ( n ) is the command registered at clock edge n , and action ( n ) is a result of com- mand ( n ). 4. all states and sequences not shown are illegal or reserved unless exp licitly described else- where in this document. 5. on self refresh exit, deselect or nop comman ds must be issued on every clock edge occur- ring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be en tered from the all banks idle state. 7. must be a legal command as defined in the command truth table, table 5 on page 29. 8. valid commands for power-down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power-down and self refresh can not be entered while read or write operations, load mode operations, or prechar g e operations are in progress. see ?power-down mode? on page 64 and see ?self refresh? on page 61 for a list of detailed restrictions. 11. minimum cke hi g h time is t cke = 3 x t ck. minimum cke low time is t cke = 3 x t ck. this requires a minimum of 3 cl ock cycles of registration. 12. the state of odt does not affect the states de scribed in this table. the odt function is not available during self refresh. see ?odt timi ng? on page 74 for more details and specific restrictions. 13. power-down modes do not perform any refresh operations. the duration of power-down mode is therefore limited by the refresh requirements. 14. ?x? means ?don?t care? (including floating around v ref ) in self refresh and power-down. however, odt must be driven hi g h or low in power-down if the odt function is enabled via emr(1). table 11: cke truth table notes 1?3, 12 current state cke command ( n ) cs#, ras#, cas#, we# action ( n ) notes previous cycle ( n -1) current cycle ( n ) power-down l l x maintain power-down 13, 14 l h deselect or nop power-down exit 4, 8 self refresh l l x maintain self refresh 14 l h deselect or nop self refresh exit 4, 5, 9 bank(s) active h l deselect or nop active power-down entry 4, 8, 10, 11 all banks idle h l deselect or nop precharge power-down entry 4, 8, 10 h l refresh self refresh entry 6, 9, 11 h h shown in table 5 on page 29 7
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 67 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode figure 46: read to power-down or self refresh entry notes: 1. power-down or self refresh entr y may occur after the read burst completes. 2. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. figure 47: read with auto precharg e to power-down or self refresh entry notes: 1. power-down or self refresh entr y may occur after the read burst completes. 2. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. d out ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 don?t care transitionin g data nop nop t3 t4 t5 valid t6 t7 t cke (min) address a10 nop cke read valid power-down 1 or self refresh entry nop 2 valid d out d out d out ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 don?t care transitionin g data nop nop t3 t4 t5 valid valid t6 t7 t cke (min) address a10 nop cke read valid power-down or self refresh 1 entry nop 2 d out d out d out d out
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 68 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode figure 48: write to power-down or self-refresh entry notes: 1. power-down or self refresh entry may occur after the write burst completes. figure 49: write with auto precharge to power-down or self refresh entry notes: 1. wr is programmed through mr[9, 10, 11] and represents ( t wr [min] ns / t ck) rounded up to next integer t ck. 2. internal prechar g e occurs at ta0 when wr has completed; power-down entry may occur 1 x t ck later at ta1, prior to t rp being satisfied. ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 don?t care transitionin g data nop nop d out t3 t4 t5 valid valid t6 valid t7 t8 t cke (min) address a10 nop cke write valid power-down or self refresh entry 1 t wtr nop 1 d out d out d out ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 don?t care transitionin g data nop nop d out t3 t4 t5 valid valid ta0 valid 2 nop ta1 ta2 t cke (min) address a10 nop cke write valid power-down or self refresh entry wr 1 indicates a break in time scale d out d out d out
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 69 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode figure 50: refresh command to power-down entry notes: 1. the earliest precharge power-down entry may occur is at t2 which is 1 x t ck after the refresh command. precharge powe r down entry occurs prior to t rfc (min) being satisfied. figure 51: active command to power-down entry notes: 1. the earliest active power-down en try may occur is at t2, which is 1 x t ck after the active command. active power-down entry occurs prior to t rcd (min) being satisfied. ck ck# command don?t care t0 t1 valid refresh t2 t3 t cke (min) cke power-down 1 entry 1 x t ck nop ck ck# command don?t care t0 t1 valid active t2 nop t3 t cke (min) cke power-down 1 entry 1 t ck address valid
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 70 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power-down mode figure 52: precharge command to power-down entry notes: 1. the earliest precharge power-down entry may occur is at t2, which is 1 x t ck after the pre- char g e command. precharge power-down entry occurs prior to t rp (min) bein g satisfied. figure 53: load mode command to power-down entry notes: 1. the earliest precharge power-do wn entry is at t3, which is after t mrd is satisfied. 2. all banks must be in the precharged state and t rp met prior to issuing lm command. 3. valid address for lm command includes mr, emr, emr(2), and emr(3) registers. ck ck# command don?t care t0 t1 valid prechar g e t2 nop t3 t cke (min) cke power-down 1 entry 1 x t ck address a10 valid all banks vs sin g le bank ck ck# command don?t care t0 t1 valid lm t2 nop t3 t4 t cke (min) cke power-down 1 entry t mrd address valid 3 t rp 2 nop
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 71 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram precharge power-down clock frequency change precharge power-down clock frequency change when the ddr2 sdram is in precharge power-down mode, odt must be turned off and cke must be at a logic low level. a minimum of two differential clock cycles must pass after cke goes low before clock frequency may change. the device input clock frequency is allowed to change only within minimum and maximum operating frequen- cies specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, new stable clocks must be provided to the device before precharge power-down may be exited, and dll must be reset via emr after precharge power-down exit. depending on the new clock frequency, an additional lm command might be required to appropriately set the wr mr[11, 10, 9]. during the dll relock period of 200 cycles, odt must remain off. after the dll lock time, the dram is ready to operate with a new clock frequency. figure 54: input clock frequency change during precharge power-down mode notes: 1. if this command is a prechar g e (or if the device is already in the idle state), then the power-down mode shown is precharge power-do wn, which is required prior to the clock frequency change. 2. a minimum of 2 x t ck is required after entering prec harge power-down prior to changing clock frequencies. 3. once the new clock frequency has chan ged and is stable, a minimum of 1 x t ck is required prior to exiting precharge power-down. 4. minimum cke hi g h time is t cke = 3 x t ck. minimum cke low time is t cke = 3 x t ck. this requires a minimum of three clock cycles of registration. ck ck# command valid 1 nop addr cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 t3 ta0 t2 don?t care valid t cke (min) 4 t cke (min) 4 t xp lm dll reset valid valid nop t ch t cl ta1 ta2 tb0 ta3 2 x t ck (min) 2 1 x t ck (min) 3 t ch t cl t ck odt 200 x t ck nop ta4 previous clock frequency new clock frequency frequency change high-z high-z indicates a break in time scale
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 72 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reset function reset function (cke low anytime) ddr2 sdram applications may go into a rese t state anytime during normal operation. if an application enters a reset condition, cke is used to ensure the ddr2 sdram device resumes normal operation after re-initial izing. all data will be lost during a reset condition; however, the ddr2 sdram device will continue to operate properly if the following conditions outlined in this section are satisfied. the reset condition defined here assumes all supply voltages (v dd , v dd q, v dd l, and v ref ) are stable and meet all dc specifications prior to, during, and after the reset operation. all other input pins of the ddr2 sdram device are a ?don?t care? during reset with the exception of cke. if cke asynchronously drops low during any valid operation (including a read or write burst), the memory controller must satisfy the timing parameter t delay before turning off the clocks. stable clocks must exis t at the ck, ck# inputs of the dram before cke is raised high, at which time the normal initialization sequence must occur. see ?initialization? on page 16. the ddr2 sdram device is now ready for normal operation after the initialization sequence. figure 55 on page 73 shows the proper sequence for a reset operation.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 73 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reset function figure 55: reset function notes: 1. either nop or desele ct command may be applied. 2. pre = prechar g e command. 3. dm represents dm for x4/x8 configuration an d udm, ldm for x16 configuration. dqs rep- resents dqs, dqs#, udqs, udqs #, ldqs, ldqs#, rdqs, rdqs# for the appropriate configu- ration (x4, x8, x16). 4. initialization timing is shown in figure 7 on page 16. 5. in certain cases where a read cy cle is interrupted, cke going hi g h may result in the com- pletion of the burst. 6. v dd , v dd l, v dd q, v tt , and v ref must be valid at all times. cke r tt ba0, ba1 high-z dm 3 dqs 3 high-z address a10 ck ck# t cl command 2 nop 1 pre all banks ta0 don?t care transitionin g data t rp a t cl t ck odt dq 3 high-z t = 400ns (min) tb0 read nop 1 t0 t1 t2 col n bank a t delay 6 d out d out read nop 1 col n bank b d out high-z high-z unknown r tt on system reset t3 t4 t5 start of normal 4 initialization sequence nop 1 indicates a break in time scale 5 t cke (min)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 74 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing odt timing once a 12ns delay ( t mod) has been satisfied, and af ter the odt function has been enabled via the emr load mode command, odt can be accessed under two timing categories. odt will operate in either synchronous mode or asynchronous mode, depending on the state of cke. odt can switch anytime except during self refresh mode and a few clocks after being enabled vi a emr, as shown in figure 56 on page 75. there are two timing categories for odt?tu rn-on and turn-off. during active mode (cke high) and fast-exit power-down mode (any row of any bank open, cke low, mr[12 = 0]), t aond, t aon, t aofd, and t aof timing parameters are applied, as shown in figure 58 on page 76 and table 12 on page 76. during slow-exit power-down mode (any row of any bank open, cke low, mr[12] = 1) and precharge power-down mode (all bank s/rows precharged and idle, cke low), t aonpd and t aofpd timing parameters are applie d, as shown in figure 59 on page 77 and table 13 on page 77. odt turn-off timing, prior to entering any power-down mode, is determined by the parameter t anpd (min), as shown in figure 60 on page 78. at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied, t aofd and t aof timing parameters apply. figure 60 on page 78 also shows the example where t anpd (min) is not satisfied since odt high does not occur until state t3. when t anpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing prior to entering any power-down mode is determined by the parameter t anpd, as shown in figure 61 on page 79. at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied, t aond and t aon timing parameters apply. figure 61 also shows the example where t anpd (min) is not satisfied since odt high does not occur until state t3. when t anpd (min) is not satisfied, t aonpd timing parameters apply. odt turn-off timing after exiting any power- down mode is determined by the parameter t axpd (min), as shown in figure 62 on page 80. at state ta1, the odt low signal satis- fies t axpd (min) after exiting power-down mode at state t1. when t axpd (min) is satis- fied, t aofd and t aof timing parameters apply. figure 62 also shows the example where t axpd (min) is not satisfied since odt low occurs at state ta0. when t axpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing after exiting either slow-exit power-down mode or precharge power-down mode is determined by the parameter t axpd (min), as shown in figure 63 on page 81. at state ta1, the odt high signal satisfies t axpd (min) after exiting power- down mode at state t1. when t axpd (min) is satisfied, t aond and t aon timing param- eters apply. figure 63 also shows the example where t axpd (min) is not satisfied since odt high occurs at state ta0. when t axpd (min) is not satisfied, t aonpd timing parameters apply.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 75 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 56: odt timing for ente ring and exiting power-down mode mrs command to odt update delay during normal operation, the value of th e effective termination resistance can be changed with an emrs set command. t mod (max) updates the r tt setting. figure 57: timing for mrs command to odt update delay notes: 1. lm command directed to mo de register, which updates the in formation in emr(1)[a6, a2], i.e., r tt (nominal). 2. to prevent any impedance glitch on the channe l, the following conditions must be met: t aofd must be met before issuing the lm co mmand; odt must remain low for the entire duration of the t mod window, until t mod is met. t anpd (3 t c ks) 1 st c ke lat c he d low t axpd (8 t c ks) 1 st c ke lat c he d high s yn c hronous appli c a b le mo d es appli c a b le timin g parameters s yn c hronous s yn c hronous or asyn c hronous any mo d e ex c ept self refresh mo d e any mo d e ex c ept self refresh mo d e a c tive power- d own fast (syn c hronous) a c tive power- d own slow (asyn c hronous) pre c har g e power- d own (asyn c hronous) t aond/ t aofd (syn c hronous) t aonpd/ t aofpd (asyn c hronous) t aond/ t aofd t aond/ t aofd c ke c k# c k odt 2 internal r tt s ettin g emr s 1 nop nop nop nop nop c md t aofd t mod ol d s ettin g un d efine d new s ettin g 0ns 2 t i s
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 76 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 58: odt timing for acti ve or fast-exit power-down mode note: the half-clock of t aofd?s 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47, for t aof (min) and 2.5 + 0.03, or 2.53, for t aof (max). table 12: ddr2-400/533 odt timing for ac tive and fast-exit power-down modes parameter symbol min max units odt turn-on delay t aond 2 2 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps t1 t0 t2 t3 t4 t5 t 6 valid valid valid valid valid valid valid c k# c k c ke t aof (max) odt r tt t aon (min) t aon (max) t aond addr t aofd t aof (min) valid valid valid valid valid valid valid c md t c h t c l t c k don ? t c are r tt unknown r tt on
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 77 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 59: odt timing for slow- exit or precharge power-down modes table 13: ddr2-400/533 odt timing for sl ow-exit and precharge power-down modes parameter symbol min max units odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps don ? t c are t1 t0 t2 t3 t4 t5 t 6 valid valid valid valid valid valid valid c k# c k c ke odt r tt addr valid valid valid valid valid valid valid c md t c h t c l t c k t aonpd (min) t aonpd (max) t aofpd (min) t aofpd (max) transitionin g r tt t7 valid valid r tt unknown r tt on
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 78 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 60: odt turn-off timing s when entering power-down mode note: the half-clock of t aofd?s 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47, for t aof (min) and 2.5 + 0.03, or 2.53, for t aof (max). table 14: ddr2-400/533 odt turn-off ti mings when entering power-down mode parameter symbol min max units odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 t ck t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck cke t anpd (min) odt r tt t aof (min) t aof (max) t aofd odt r tt t aofpd (min) t aofpd (max) don?t care transitioning r tt r tt unknown rtt on
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 79 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 61: odt turn-on timing when entering power-down mode table 15: ddr2-400/533 odt turn-on timi ng when entering power-down mode parameter symbol min max units odt turn-on delay t aond 2 2 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 t ck t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck cke t anpd (min) odt r tt t aon (min) t aon (max) t aond odt r tt t aonpd (min) t aonpd (max) don?t care transitioning r tt r tt unknown r tt on
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 80 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 62: odt turn-off timing when exiting power-down mode note: the half-clock of t aofd?s 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47, for t aof (min) and 2.5 + 0.03, or 2.53, for t aof (max). table 16: ddr2-400/533 odt turn-off ti ming when exiting power-down mode parameter symbol min max units odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down exit latency t axpd 8 t ck t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) odt r tt t aof (max) odt r tt t aofpd (min) t aofpd (max) command t cke (min) ta2 ta3 ta4 ta5 nop nop nop nop don?t care transitioning rtt rtt unknown rtt on t aof (min) t aofd indicates a break in time scale
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 81 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram odt timing figure 63: odt turn-on timing when exiting power-down mode table 17: ddr2-400/533 odt turn-on ti ming when exiting power-down mode parameter symbol min max units odt turn-on delay t aond 2 2 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt to power-down exit latency t axpd 8 t ck t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) command ta2 ta3 ta4 ta5 nop nop nop nop odt rtt t aon (min) t aon (max) t aond odt r tt t aonpd (min) t aonpd (max) don?t care transitioning r tt r tt unknown r tt on indicates a break in time scale t cke (min)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 82 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram absolute maximum ratings absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. v dd , v dd q, and v dd l must be within 300mv of each other at all times. 2. v ref 0.6 x v dd q; however, v ref may be v dd q provided that v ref 300mv. 3. voltage on any i/o may not exceed voltage on v dd q. temperature and thermal impedance it is imperative that the ddr2 sdram devi ce?s temperature specifications, shown in table 18 on page 83, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in main- taining the proper junction temperature is using the device?s thermal impedances correctly. the thermal impedances are listed in table 19 on page 83 for the applicable and available die revision and packages. incorrectly using thermal impedances can produce significant errors. read micron technical note tn-00-08, ?thermal applications,? prior to using the thermal imped- ances listed below. for designs that are expe cted to last several years and require the flexibility to use several designs, consider using final target theta values, rather than existing values, to account for larger thermal impedances. the ddr2 sdram device?s safe junction temperature range can be maintained when the t c specification is not exceeded. in applic ations where the device?s ambient temper- ature is too high, use of forced air and/or he at sinks may be required in order to satisfy the case temperature specifications. table 17: absolute maximum dc ratings parameter symbol min max units notes v dd supply voltage relative to v ss v dd ?1.0 2.3 v 1 v dd q supply voltage relative to v ss q v dd q ?0.5 2.3 v 1, 2 v dd l supply voltage relative to v ss l v dd l?0.5 2.3 v 1 voltage on any ball relative to v ss v in , v out ?0.5 2.3 v 3 input leakage current; any input 0v v in v dd ; all other balls not under test = 0v) i i ?5 5 a output leakage current; 0v v out v dd q; dq and odt disabled i oz ?5 5 a v ref leakage current; v ref = valid v ref level i v ref ?2 2 a
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 83 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram temperature and thermal impedance notes: 1. max storage case temperature; t st g is measured in the center of the package, as shown in figure 64. this case temperatur e limit is allowed to be exce eded briefly during package reflow, as noted in micron technical note , tn-00-15, ?recommended soldering parame- ters.? 2. max operating case temperature; t c is measured in the center of the package, as shown in figure 64. 3. device functionality is not guarant eed if the device exceeds maximum t c during operation. 4. both temperature specific ations must be satisfied. 5. operating ambient temperat ure surrounding the package. notes: 1. thermal resistance data is based on a numb er of samples from multiple lots and should be viewed as a typical number. 2. this is an estimate; simulated nu mber and actual results could vary. figure 64: example temperature test point location ta bl e 1 8 : te mp er a t ure l im it s parameter symbol min max units notes storage temperature t st g ?55 100 c 1 operating temperature ? commercial t c 085c2, 3 operating temperature ? industrial t c ?40 95 c 2, 3, 4 t amb ?40 85 c 4, 5 table 19: thermal impedance die rev package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) b 1 60-ball 2-layer 53.2 40.0 37.2 27.5 2.9 4-layer 37.4 30.9 27.7 24.2 84-ball 2-layer 50.2 36.8 32.1 24.5 3.1 4-layer 34.9 28.0 25.5 21.3 c 1 60-ball 2-layer 56.9 43.6 38.5 30.6 3.8 4-layer 40.6 34.1 31.3 27.0 84-ball 2-layer 56.8 42.8 37.7 24.8 3.9 4-layer 40.3 33.2 30.4 23.5 last shrink target 2 60-ball 2-layer 60.0 48.0 45.0 32.0 5.0 4-layer 42.0 36.0 34.0 29.0 84-ball 2-layer 59.0 45.0 40.0 27.0 5.2 4-layer 44.0 35.0 34.0 26.0 12.00 6 .00 12.50 6 .75 12mm x 12.5 mm ?cc? fbga test point 10.00 5.00 12.50 6 .75 10mm x 12.5 mm ? bn ? fbga test point 12.00 6 .00 10.00 5.00 12mm x 10 mm ?c b ? fbga test point 10.00 5.00 10.00 5.00 10mm x 10mm ? b 6? fbga test point
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 84 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac and dc operating conditions ac and dc operating conditions notes: 1. v dd and v dd q must track each other. v dd q must be v dd . 2. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak-to-pe ak noise (non-common mode) on v ref may not exceed 1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref ( dc ). this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied direct ly to the device. v tt is a system supply for signal termination resis- tors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v dd q tracks with v dd ; v dd l tracks with v dd . 5. v ss q = v ss l = v ss . notes: 1. r tt 1( eff ) and r tt 2( eff ) are determined by separately applying v ih ( ac ) and v il ( ac ) to the ball being tested, and then measuring current, i(v ih ( ac )), and i(v il ( ac )), respectively. 2. measure voltage (vm) at tested ball with no load. 3. it device minimum values are derated by si x percent when device operates between ?40c and 0c (t c ). table 20: recommended dc op erating conditions (sstl_18) all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1, 5 v dd l supply voltage v dd l 1.7 1.8 1.9 v 4, 5 i/o supply voltage v dd q 1.7 1.8 1.9 v 4, 5 i/o reference voltage v ref ( dc ) 0.49 x v dd q 0.50 x v dd q0.51 x v dd qv 2 i/o termination voltage (system) v tt v ref ( dc ) - 40 v ref ( dc )v ref ( dc ) + 40 mv 3 table 21: odt dc electrical characteristics all voltages referenced to v ss parameter symbol min nom max units notes r tt effective impedance value for 75 setting emr (a6, a2) = 0, 1 r tt 1( eff )60 75 90 1, 3 r tt effective impedance value for 150 setting emr (a6, a2) = 1, 0 r tt 2( eff ) 120 150 180 1, 3 r tt effective impedance value for 50 setting emr (a6, a2) = 1, 1 r tt 3( eff )40 50 60 1, 3 deviation of vm with respect to v dd q/2 vm ?6 6 % 2 r tt eff () v ih ac () v il ac () ? iv ih ac () () iv il ac () () ? ------------------------------------------------------------- = vm 2 vm v dd q ----------------- - 1 ? ?? ?? 100 =
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 85 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions input electrical characterist ics and operating conditions figure 65: single-ended input signal levels note: numbers in diagram reflect nominal values. table 22: input dc logic levels all voltages referenced to v ss parameter symbol min max units input hi g h (logic 1) voltage v ih ( dc )v ref ( dc ) + 125 v dd q + 300 mv input low (logic 0) voltage v il ( dc ) ?300 v ref ( dc ) - 125 mv table 23: input ac logic levels all voltages referenced to v ss parameter symbol min max units input hi g h (logic 1) voltage (-5e/-37e) v ih ( ac )v ref ( dc ) + 250 ? mv input hi g h (logic 1) voltage (-3/-3e/-25/-25e) v ih ( ac )v ref ( dc ) + 200 ? mv input low (logic 0) voltage (-5e/-37e) v il ( ac )?v ref ( dc ) - 250 mv input low (logic 0) vo ltage (-3/-3e/-25/-25e) v il ( ac )?v ref ( dc ) - 200 mv 650mv 775mv 864mv 882mv 900mv 918mv 936mv 1,025mv 1,150mv v il(ac) v il(dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih(dc) v ih(ac)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 86 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions notes: 1. v in ( dc ) specifies the allowable dc execution of each input of differential pair such as ck, ck#, dqs, dqs#, ldqs, ldqs#, udqs, udqs#, and rdqs, rdqs#. 2. v id ( dc ) specifies the input differential voltage | v tr - v cp | required for sw itching, where v tr is the true input (such as ck, dqs, ldqs, udqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#). the minimum value is equal to v ih ( dc ) - v il ( dc ). differ- ential input signal leve ls are shown in figure 66. 3. v id ( ac ) specifies the input differential voltage | v tr - v cp | required for sw itching, where v tr is the true input (such as ck, dq s, ldqs, udqs, rdqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#, rdqs#). the minimum value is equal to v ih ( ac ) - v il ( ac ), as shown in table 23 on page 85. 4. the typical value of v ix ( ac ) is expected to be about 0.5 x v dd q of the transmitting device and v ix ( ac ) is expected to track variations in v dd q. v ix ( ac ) indicates the voltage at which differential input si gnals must cross, as shown in figure 66. 5. v mp ( dc ) specifies the input differen tial common mode voltage (v tr + v cp )/2 where v tr is the true input (ck, dqs) level and v cp is the complementary input (ck#, dqs#). v mp ( dc ) is expected to be approximately 0.5 x v dd q. figure 66: differential input signal levels notes: 1. this provides a minimum of 850mv to a maximum of 950mv and is expected to be v dd q/2. 2. tr and cp must cross in this region. 3. tr and cp must meet at least v id ( dc ) min when static and is centered around v mp (dc). 4. tr and cp must have a mini mum 500mv peak-to-peak swing. 5. tr and cp may not be more positive than v dd q + 0.3v or more negative than v ss - 0.3v. 6. for ac operation, all dc clock requirements must also be satisfied. 7. numbers in diagram re flect nominal values (v dd q = 1.8v). 8. tr represents the ck, dqs, rdqs, ldqs, and udqs signals; cp represents ck#, dqs#, rdqs#, ldqs#, and udqs# signals. table 24: differential input logic levels all voltages referenced to v ss parameter symbol min max units notes dc input signal voltage v in ( dc )?300 v dd q + 300 mv 1 dc differential input voltage v id ( dc ) 250 v dd q + 600 mv 2 ac differential input voltage v id ( ac ) 500 v dd q + 600 mv 3 ac differential cr oss-point voltage v ix ( ac ) 0.50 x v dd q - 175 0.50 x v dd q + 175 mv 4 input midpoint voltage v mp ( dc ) 850 950 mv 5 tr 8 cp 8 2.1v @ v dd q = 1. 8 v 2 3 v in(dc) max 5 v in(dc) min 5 4 - 0.30v 0.9v 1.075v 0.725 v v id(ac) v id(dc) x v mp(dc) 1 v ix(ac) x
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 87 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions notes: 1. all voltages referenced to v ss . 2. input waveform setup timing ( t is b ) is referenced from the input signal crossing at the v ih ( ac ) level for a rising signal and v il ( ac ) for a falling signal applied to the device under test, as shown in figure 75 on page 102. 3. input waveform hold ( t ih b ) timing is referenced from the input signal crossing at the v il ( dc ) level for a rising signal and v ih ( dc ) for a falling signal applied to the device under test, as shown in figure 75 on page 102. 4. input waveform setup timing ( t ds) and hold timing ( t dh) for single-ended data strobe is referenced from the crossing of dqs, udqs, or ldqs through the v ref level applied to the device under test, as shown in figure 77 on page 103. 5. input waveform setup timing ( t ds) and hold timing ( t dh) when differential data strobe is enabled is referenced from the cross-point of dqs/dqs#, udqs/udqs#, or ldqs/ldqs#, as shown in figure 76 on page 102. 6. input waveform timing is referenc ed to the crossi ng point level (v ix ) of two input signals (v tr and v cp ) applied to the device under test, where v tr is the ?true? in put signal and v cp is the complementary input signal, as shown in figure 78 on page 103. 7. see ?input slew rate derating? on page 88. 8. the slew rate for single-ended in puts is measured from dc -level to ac-level, (v il ( dc ) to v ih ( ac ) on the rising edge and v il ( ac ) to v ih ( dc ) on the falling edge. for signals referenced to v ref , the valid intersection is where the ?tangent? line intersects v ref , as shown in figures 68, 70, 72, and 74. 9. the slew rate for differentia lly ended inputs is measured from twice the dc-level to twice the ac-level: 2 x v il ( dc ) to 2 x v ih ( ac ) on the rising edge and 2 x v il ( ac ) to 2 x v ih ( dc ) on the falling edge). for example, the ck/ck# would be ?250mv to +500mv for ck rising edge and would be +250mv to ?500mv for ck falling edge. table 25: ac input test conditions parameter symbol min max units notes input setup timing measurement reference level ba1?ba0, a0?a12 a0?a13 (a12 x16), cs#, ras#, cas#, we#, odt, dm, udm, ldm, and cke v rs see note 2 1, 2, 7, 8 input hold timing meas urement reference level ba1?ba0, a0?a13 (a12 x16), cs#, ras#, cas#, we#, odt, dm, udm, ldm, and cke v rh see note 3 1, 3, 7, 8 input timing measurement refe rence level (single-ended) dqs for x4, x8; udqs, ldqs for x16 v ref ( dc )v dd q x 0.49 v dd q x 0.51 v 1, 4, 7, 8 input timing measurement re ference level (differential) ck, ck# for x4, x8, x16 dqs, dqs# for x4, x8; rdqs, rdqs# for x8 udqs, udqs#, ldqs, ldqs# for x16 v rd v ix ( ac ) v 1, 5, 6, 7, 9
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 88 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating input slew rate derating for all input signals, the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is (base) and t ih (base) value to the t is and t ih derating value, respectively. example: t is (total setup time) = t is (base) + t is. t is, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. setup nominal slew rate ( t is) for a falling signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first cros sing of v il ( ac ) max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref ( dc ) to ac region,? use nominal slew rate for derating value (figure 67 on page 90). if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref ( dc ) to ac region,? the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 68 on page 91). t ih, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of v il ( dc ) max and the first crossing of v ref ( dc ). t ih, nominal slew rate for a falling signal, is defined as the slew rate between the last crossing of v ih ( dc ) min and the first cros sing of v ref ( dc ). if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref ( dc ) region,? use nominal slew rate for derating value (figure 69 on page 92). if the actual signal is earlier than the nomi nal slew rate line anywhere between shaded ?dc to v ref ( dc )) region,? the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for the derating value (figure 70 on page 93). although the total setup time might be negative for slow slew rates (a valid input signal will not have reached v ih ( ac )/v il ( ac ) at the time of the rising clock transition), a valid input signal is still required to complete the transition and reach v ih ( ac )/v il ( ac ). for slew rates in between the values listed in tables 26 and 27, the derating values may obtained by linear interpolation.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 89 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating table 26: ddr2-400/533 setup and hold time derating values ( t is and t ih) command/ address slew rate (v/ns) ck, ck# differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns t is t ih t is t ih t is t ih 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 ?11 ?14 +19 +16 +49 +46 ps 0.8 ?25 ?31 +5 ?1 +35 +29 ps 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 0.1 ?1450 ?1125 ?1420 ?1095 ?1390 ?1065 ps table 27: ddr2-667 setup and hold time derating values ( t is and t ih) command/ address slew rate (v/ns) ck, ck# differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns t is t ih t is t ih t is t ih 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +160 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 ?5 ?14 +25 +16 +55 +46 ps 0.8 ?13 ?31 +17 ?1 +47 +29 ps 0.7 ?22 ?54 +8 ?24 +38 +6 ps 0.6 ?34 ?83 ?4 ?53 +36 ?23 ps 0.5 ?60 ?125 ?30 ?95 0 ?65 ps 0.4 ?100 ?188 ?70 ?158 ?40 ?128 ps 0.3 ?168 ?292 ?138 ?262 ?108 ?232 ps 0.25 ?200 ?375 ?170 ?345 ?140 ?315 ps 0.2 ?325 ?500 ?295 ?470 ?265 ?440 ps 0.15 ?517 ?708 ?487 ?678 ?457 ?648 ps 0.1 ?1,000 ?1,125 ?970 ?1,095 ?940 ?1,065 ps
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 90 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 67: nominal slew rate for t is v ss c k# c k t ih t i s t ih s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr tf = v ih ( a c ) min - v ref ( d c ) tr = v dd q t i s nominal slew rate v ref to a c re g ion v ref to a c re g ion v ref ( d c ) - v il ( a c ) max v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min nominal slew rate
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 91 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 68: tangent line for t is s etup slew rate risin g si g nal tf tr tan g ent line [v ih ( a c ) min - v ref ( d c )] tr = tan g ent line tan g ent line v ref to a c re g ion nominal line nominal line t ih t i s t ih t i s v ss c k# c k v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max v ref to a c re g ion
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 92 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 69: nominal slew rate for t ih tr tf nominal slew rate d c to v ref re g ion t ih t i s t i s v ss c k# c k v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion nominal slew rate t ih
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 93 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 70: tangent line for t ih tan g ent line d c to v ref re g ion t ih t i s t i s v ss v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion tan g ent line t ih c k c k# hol d slew rate fallin g si g nal tf tr tan g ent line [v ih ( d c ) min - v ref ( d c )] tf = nominal line hol d slew rate risin g si g nal tan g ent line [v ref ( d c ) - v il ( d c ) max] tr = nominal line
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 94 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating notes: 1. for all input signals, the total t ds and t dh required is calculated by adding the data sheet value to the derating value listed in table 28. 2. t ds nominal slew rate for a rising signal is defi ned as the slew rate be tween the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. t ds nominal slew rate for a falling signal is defined as the slew rate betw een the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always earlier than the no minal slew rate line between shaded ?v ref ( dc ) to ac region,? use nominal slew rate for derating value (see figure 71). if the actual signal is later than the nomina l slew rate line anywhere between shaded ?v ref ( dc ) to ac region,? the slew rate of a tang ent line to the actual signal from the ac level to dc level is used for derating value (see figure 72). 3. t dh nominal slew rate for a rising signal is de fined as the slew rate between the last cross- ing of v il ( dc ) max and the first crossing of v ref ( dc ). t dh nominal slew rate for a falling sig- nal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first crossing of v ref (dc). if the actual signal is always late r than the nominal slew rate line between shaded ?dc level to v ref ( dc ) region,? use nominal slew rate for derating value (see figure 73). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref ( dc ) region,? the slew rate of a tangen t line to the actual signal from the dc level to v ref ( dc ) level is used for derating value (see figure 74). 4. although the total setup time might be negative for slow sl ew rates (a valid input signal will not have reached v ih ( ac )/v il ( ac ) at the time of the rising clock transition), a valid input signal is still requir ed to complete the transition and reach v ih ( ac )/v il ( ac ). 5. for slew rates between the values listed in th is table, the derating values may be obtained by linear interpolation. 6. these values are typically not subject to production test. they are verified by design and characterization. 7. single-ended dqs requires special derating . the values in table 30 are the dqs single- ended slew rate derating with dqs referenced at v ref and dq referenced at the logic levels t ds b and t dh b . table 31 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-667. table 32 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-533. table 33 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-400. table 28: ddr2-400/533 t ds, t dh derating values with differential strobe notes: 1?7; all units in ps dq slew rate (v/ns) dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0125451254512545???????????? 1.5 8321832183219533 ? ? ? ? ? ? ? ? ? ? 1.0 00000012122424???????? 0.9 ? ? ?11 ?14 ?11 ?14 1 ?2 13 10 25 22 ? ? ? ? ? ? 0.8 ? ? ? ? ?25 ?31 ?13 ?19 ?1 ?7 11 5 23 17 ? ? ? ? 0.7 ???????31?42?19?30?7?185?6176?? 0.6 ? ? ? ? ? ? ? ? ?43 ?59 ?31 ?47 ?19 ?35 ?7 ?23 5 ?11 0.5 ? ? ? ? ? ? ? ? ? ? ?74 ?89 ?62 ?77 ?50 ?65 ?38 ?53 0.4 ? ? ? ? ? ? ? ? ? ? ? ? ?127 ?140 ?115 ?128 ?103 ?116
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 95 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating notes: 1. for all input signals the total t ds and t dh required is calculated by adding the data sheet value to the derating value listed in table 29. 2. t ds nominal slew rate for a rising signal is defi ned as the slew rate be tween the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. t ds nominal slew rate for a falling signal is defined as the slew rate betw een the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always earlier than the no minal slew rate line between shaded ?v ref ( dc ) to ac region,? use nominal slew rate for derating value (see figure 71). if the actual signal is later than the nomina l slew rate line anywhere between shaded ?v ref ( dc ) to ac region,? the slew rate of a tang ent line to the actual signal from the ac level to dc level is used for derating value (see figure 72). 3. t dh nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il ( dc ) max and the first crossing of v ref ( dc ). t dh nominal slew rate for a falling signal is defined as th e slew rate between the last crossing of v ih ( dc ) min and the first crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to v ref ( dc ) region,? use nominal slew rate for derating value (see figure 73). if the actual signal is earlie r than the nominal slew rate line anywhere between shaded ?dc to v ref ( dc ) region,? the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for derati ng value (see figure 74). 4. although the total setup time might be negative for slow sl ew rates (a valid input signal will not have reached v ih ( ac )/v il ( ac ) at the time of the rising clock transition), a valid input signal is still requir ed to complete the transition and reach v ih ( ac )/v il ( ac ). 5. for slew rates between the values listed in th is table, the derating values may be obtained by linear interpolation. 6. these values are typically not subject to production test. they are verified by design and characterization. 7. single-ended dqs requires special derating . the values in table 30 are the dqs single- ended slew rate derating with dqs referenced at v ref and dq referenced at the logic levels t ds b and t dh b . table 31 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-667. table 32 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-533. table 33 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-400. table 29: ddr2-667 t ds, t dh derating values with differential strobe notes: 1?7; all units in ps dq slew rate (v/ns) dqs, dqs# differential slew rate 2.8 v/ns 2.4 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135 1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114 1.0 0 0 0 0 0 0 121224243636484860607272 0.9 ?5?14?5?14?5?147 ?219103122433455466758 0.8 ?13 ?31 ?13 ?31 ?13 ?31 ?1 ?19 11 ?7 23 5 35 17 47 29 59 41 0.7 ?22 ?54 ?22 ?54 ?22 ?54 ?10 ?42 2 ?30 14 ?18 26 ?6 38 6 50 18 0.6 ?34 ?83 ?34 ?83 ?34 ?83 ?22 ?71 ?10 ?59 2 ?47 14 ?35 26 ?23 38 ?11 0.5 ?60 ?125 ?60 ?125 ?60 ?125 ?48 ?113 ?36 ?101 ?24 ?89 ?12 ?77 0 ?65 12 ?53 0.4 ?100 ?188 ?100 ?188 ?100 ?188 ?88 ?176 ?76 ?164 ?64 ?152 ?52 ?140 ?40 ?128 ?28 ?116
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 96 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating notes: 1. derating values, to be used with base t ds b - and t dh b -specified values. table 30: single-ended dqs slew rate derating values using t ds b and t dh b reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38 1.59732973297329732973211227122241322014217 1 30?1030?1030?1030?1030?10 45 ?15 55 ?18 65 ?22 75 ?25 0.9 25 ?24 25 ?24 25 ?24 25 ?24 25 ?24 40 ?29 50 ?32 60 ?36 70 ?39 0.8 17 ?41 17 ?41 17 ?41 17 ?41 17 ?41 32 ?46 42 ?49 52 ?53 61 ?56 0.7 5 ?64 5 ?64 5 ?64 5 ?64 5 ?64 20 ?69 30 ?72 40 ?75 50 ?79 0.6 ?7 ?93 ?7 ?93 ?7 ?93 ?7 ?93 ?7 ?93 8 ?98 18 ?102 28 ?105 38 ?108 0.5 ?28 ?135 ?28 ?135 ?28 ?135 ?28 ?135 ?28 ?135 ?13 ?140 ?3 ?143 7 ?147 17 ?150 0.4 ?78 ?198 ?78 ?198 ?78 ?198 ?78 ?198 ?78 ?198 ?63 ?203 ?53 ?206 ?43 ?210 ?33 ?213 table 31: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-667 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276 1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275 1 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275 0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275 0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275 0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275 0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275 0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275 0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 97 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating table 32: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-533 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326 1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325 1 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325 0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325 0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325 0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325 0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325 0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325 0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324 table 33: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-400 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376 1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375 1 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375 0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375 0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375 0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375 0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375 0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375 0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 98 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 71: nominal slew rate for t ds notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. v ref to a c re g ion v ref to a c re g ion s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr v ref ( d c ) - v il ( a c ) max tf = v ih ( a c ) min - v ref ( d c ) tr = nominal slew rate v ss dq s # 1 dq s 1 v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min t dh t d s nominal slew rate t dh t d s
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 99 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 72: tangent line for t ds notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. tf tr s etup s lew rate risin g s i g nal s etup s lew rate fallin g s i g nal tan g ent line [v ref ( d c ) - v il ( a c ) max] tf = tan g ent line [v ih ( a c ) min - v ref ( d c )] tr = t dh t d s t dh t d s v ss dq s # 1 dq s 1 v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min nominal line tan g ent line nominal line tan g ent line v ref to a c re g ion v ref to a c re g ion
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 100 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 73: nominal slew rate for t dh notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. hol d slew rate fallin g si g nal hol d slew rate risin g si g nal v ref ( d c ) - v il ( d c ) max tr = v ih ( d c ) min - v ref ( d c ) tf = tr tf nominal slew rate d c to v ref re g ion t ih t i s t i s v ss dq s # 1 dq s 1 v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion nominal slew rate t ih
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 101 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 74: tangent line for t dh notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. tan g ent line d c to v ref re g ion t ih t i s t i s v ss v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion tan g ent line t ih dq s 1 dq s # 1 hol d s lew rate fallin g s i g nal tf tr tan g ent line [v ih ( d c ) min - v ref ( d c )] tf = nominal line hol d s lew rate risin g s i g nal tan g ent line [v ref ( d c ) - v il ( d c ) max] tr = nominal line
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 102 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 75: ac input test signal waveform command/address balls figure 76: ac input test signal wavefor m for data with dqs, dqs# (differential) v ref (dc) v il (dc) max v il (ac) max v ss q v ih (dc) min v ih (ac) min v dd q v swin g (max) t is a logic levels v ref levels t ih a t is a t ih a t is b t ih b t is b t ih b ck# ck v swin g (max) dqs# dqs t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b logic levels v ref levels v ref(dc) v il(dc) max v il(ac) max v ss q v ih(dc) min v ih(ac) min v dd q
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 103 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram input slew rate derating figure 77: ac input test signal waveform for data with dqs (single-ended) figure 78: ac input test signal waveform (differential) v swin g (max) dqs v ref v ref(dc) v il(dc) max v il(ac) max v ss q v ih(dc) min v ih(ac) min v dd q logic levels v ref levels v ref levels t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b v tr v s wing v c p v dd q v ss q v ix c rossin g point
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 104 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram power and ground clamp characteristics power and ground clamp characteristics power and ground clamps are provided on th e following input-only balls: ba1?ba0, a0? a13 (a12 x16), cs#, ras#, cas#, we#, odt, and cke. figure 79: input clamp characteristics table 34: input clamp characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 volta g e a c ross c lamp (v) minimum c lamp c urrent (ma) 25.0 20.0 15.0 10.0 5.0 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 105 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac overshoot/undershoot specification ac overshoot/undershoot specification some revisions will support the 0.9v maxi mum average amplitude instead of the 0.5v maximum average amplitude that is shown in table 35 and table 36. figure 80: overshoot figure 81: undershoot table 35: address and control balls applies to ba1?ba0, a0?a13 (a12 x16) , cs#, ras#, cas#, we#, cke, odt parameter specification -5e -37e -3/-3e -25/-25e maximum peak amplitude allowed fo r overshoot area (see figure 80) 0.50v 0.50v 0.50v 0.50v maximum peak amplitude allowed for undershoot area (see figure 81) 0.50v 0.50v 0.50v 0.50v maximum overshoot area above v dd (see figure 80) 1.33 vns 1.00 vns 0.80 vns 0.66 vns maximum undershoot area below v ss (see figure 81) 1.33 vns 1.00 vns 0.80 vns 0.66 vns table 36: clock, data, strobe, and mask balls applies to dq, dqs, dqs#, rdqs, rdqs#, udqs, udqs#, ldqs, ldqs#, dm, udm, ldm parameter specification -5e -37e -3/-3e -25/-25e maximum peak amplitude allowed fo r overshoot area (see figure 80) 0.50v 0.50v 0.50v 0.50v maximum peak amplitude allowed for undershoot area (see figure 81) 0.50v 0.50v 0.50v 0.50v maximum overshoot area above v dd q (see figure 80) 0.38 vns 0.28 vns 0.23 vns 0.19 vns maximum undershoot area below v ss q (see figure 81) 0.38 vns 0.28 vns 0.23 vns 0.19 vns overshoot area maximum amplitu d e v ss / v ss q volts (v ) time (ns) v dd /v dd q un d ershoot area maximum amplitu d e v ss / v ss q volts (v) time (ns)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 106 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram output electrical characteristics and operating conditions output electrical characteris tics and operating conditions notes: 1. the typical value of v ox ( ac ) is expected to be about 0.5 x v dd q of the transmitting device and v ox ( ac ) is expected to track variations in v dd q. v ox ( ac ) indicates the voltage at which differential output signals must cross. figure 82: differential output signal levels table 37: differential ac output parameters parameter symbol min max units notes ac differential cross-point voltage v ox ( ac ) 0.50 x v dd q - 125 0.50 x v dd q + 125 mv 1 ac differential voltage swing v swin g 1.0 mv v tr v swin g v cp v dd q v ss q v ox crossing point
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 107 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram output electrical characteristics and operating conditions notes: 1. for i oh ( dc ); v dd q = 1.7v, v out = 1,420mv. (v out - v dd q)/i oh must be less than 21 for val- ues of v out between v dd q and v dd q - 280mv. 2. for i ol ( dc ); v dd q = 1.7v, v out = 280mv. v out /i ol must be less than 21 for values of v out between 0v and 280mv. 3. the dc value of v ref applied to the receiving device is set to v tt . 4. the values of i oh ( dc ) and i ol ( dc ) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih (min) plus a noise margin and v il (max) minus a noise ma rgin are delivered to an sstl_18 receiver. the actual current val- ues are derived by shifting the desired driver operating point (see output iv curves) along a 21 load line to define a convenient driver current for measurement. notes: 1. absolute specifications: 0c t c +85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v. 2. impedance measurement conditions for output source dc current: v dd q = 1.7v; v out = 1,420mv; (v out - v dd q)/i oh must be less than 23.4 for values of v out between v dd q and v dd q - 280mv. impedance measurement condit ion for output sink dc current: v dd q = 1.7v; v out = 280mv; v out /i ol must be less than 23.4 for values of v out between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage. 4. output slew rate for falling and rising edges is measured between v tt - 250mv and v tt + 250mv for single-ended signals. for differential signals (dqs - dqs#), output slew rate is measured between dqs - dqs# = ?500mv and dq s# - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. 5. the absolute value of the sl ew rate as measured from v il ( dc ) max to v ih ( dc ) min is equal to or greater than the slew rate as measured from v il ( ac ) max to v ih ( ac ) min. this is guaran- teed by design and characterization. 6. it devices require an additional 0.4 v/ns in the max limit when t c is between ?40c and 0c. figure 83: output slew rate load table 38: output dc current drive parameter symbol value units notes output minimum source dc current i oh ?13.4 ma 1, 2, 4 output minimum sink dc current i ol 13.4 ma 2, 3, 4 table 39: output characteristics parameter min nom max units notes output impedance see ?full strength pull-down driver characteristics? on page 108 1, 2 pull-up and pull-down mismatch 04 1, 2, 3 output slew rate 1.5 5 v/ns 1, 4, 5, 6 output (v out ) referen c e point 25 v tt = v dd q/2
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 108 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram full strength pull-down driver characteristics full strength pull-down driver characteristics figure 84: full strength pull-down characteristics table 40: full strength pull-down current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 0.00 0.1 4.3 5.63 7.95 0.2 8.6 11.3 15.90 0.3 12.9 16.52 23.85 0.4 16.9 22.19 31.80 0.5 20.4 27.59 39.75 0.6 23.28 32.39 47.70 0.7 25.44 36.45 55.55 0.8 26.79 40.38 62.95 0.9 27.67 44.01 69.55 1.0 28.38 47.01 75.35 1.1 28.96 49.63 80.35 1.2 29.46 51.71 84.55 1.3 29.90 53.32 87.95 1.4 30.29 54.9 90.70 1.5 30.65 56.03 93.00 1.6 30.98 57.07 95.05 1.7 31.31 58.16 97.05 1.8 31.64 59.27 99.05 1.9 31.96 60.35 101.05 pull-down characteristics 0.00 20.00 40.00 60.00 80.00 100.00 120.00 0.0 0.5 1.0 1.5 v out (v) i out (ma)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 109 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram full strength pull-up driver characteristics full strength pull-up dr iver characteristics figure 85: full strength pull-up characteristics table 41: full strength pull-up current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 0.00 0.1 ?4.3 ?5.63 ?7.95 0.2 ?8.6 ?11.3 ?15.90 0.3 ?12.9 ?16.52 ?23.85 0.4 ?16.9 ?22.19 ?31.80 0.5 ?20.4 ?27.59 ?39.75 0.6 ?23.28 ?32.39 ?47.70 0.7 ?25.44 ?36.45 ?55.55 0.8 ?26.79 ?40.38 ?62.95 0.9 ?27.67 ?44.01 ?69.55 1.0 ?28.38 ?47.01 ?75.35 1.1 ?28.96 ?49.63 ?80.35 1.2 ?29.46 ?51.71 ?84.55 1.3 ?29.90 ?53.32 ?87.95 1.4 ?30.29 ?54.90 ?90.70 1.5 ?30.65 ?56.03 ?93.00 1.6 ?30.98 ?57.07 ?95.05 1.7 ?31.31 ?58.16 ?97.05 1.8 ?31.64 ?59.27 ?99.05 1.9 ?31.96 ?60.35 ?101.05 pull-up characteristics -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 0.0 0.5 1.0 1.5 v dd q - v out (v) i out (ma)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 110 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reduced strength pull-down driver characteristics reduced strength pull-down driver characteristics figure 86: reduced strength pull-down characteristics table 42: reduced strength pull-down current (ma) voltage (v) minimum nominal maximum 0.0 0.000.000.00 0.1 1.722.984.77 0.2 3.445.999.54 0.3 5.16 8.75 14.31 0.4 6.76 11.76 19.08 0.5 8.16 14.62 23.85 0.6 9.31 17.17 28.62 0.7 10.18 19.32 33.33 0.8 10.72 21.40 37.77 0.9 11.07 23.32 41.73 1.0 11.35 24.92 45.21 1.1 11.58 26.30 48.21 1.2 11.78 27.41 50.73 1.3 11.96 28.26 52.77 1.4 12.12 29.10 54.42 1.5 12.26 29.70 55.80 1.6 12.39 30.25 57.03 1.7 12.52 30.82 58.23 1.8 12.66 31.41 59.43 1.9 12.78 31.98 60.63 pull-down characteristics 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 0.0 0.5 1.0 1.5 v out (v) i out (ma)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 111 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram reduced strength pull-up driver characteristics reduced strength pull-up driver characteristics figure 87: reduced strength pull-up characteristics table 43: reduced strength pull-up current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 0.00 0.1 ?1.72 ?2.98 ?4.77 0.2 ?3.44 ?5.99 ?9.54 0.3 ?5.16 ?8.75 ?14.31 0.4 ?6.76 ?11.76 ?19.08 0.5 ?8.16 ?14.62 ?23.85 0.6 ?9.31 ?17.17 ?28.62 0.7 ?10.18 ?19.32 ?33.33 0.8 ?10.72 ?21.40 ?37.77 0.9 ?11.07 ?23.32 ?41.73 1.0 ?11.35 ?24.92 ?45.21 1.1 ?11.58 ?26.30 ?48.21 1.2 ?11.78 ?27.41 ?50.73 1.3 ?11.96 ?28.26 ?52.77 1.4 ?12.12 ?29.10 ?54.42 1.5 ?12.26 ?29.69 ?55.8 1.6 ?12.39 ?30.25 ?57.03 1.7 ?12.52 ?30.82 ?58.23 1.8 ?12.66 ?31.42 ?59.43 1.9 ?12.78 ?31.98 ?60.63 pull-up characteristics -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.0 0.5 1.0 1.5 v dd q - v out (v) i out (ma)
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 112 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram fbga package capacitance fbga package capacitance notes: 1. this parameter is sampled. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f = 100 mhz, t c = 25c, v out ( dc ) = v dd q/2, v out (peak-to-peak) = 0.1v. dm input is grouped with i/o balls, reflecting the fact that they are matched in loading. 2. the input capacitance per ball group will not di ffer by more than th is maximum amount for any given device. 3. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 4. reduce max limit by 0.5pf fo r -3/-3e/-25/-25e speed devices. 5. reduce max limit by 0.25pf for -3/-3e/-25/-25e speed devices. table 44: input capacitance parameter symbol min max units notes input capacitance: ck, ck# cck 1.0 2.0 pf 1 delta input capacitance: ck, ck# cdck ? 0.25 pf 2 input capacitance: ba1?ba0, a0?a13 (a12 x16), cs#, ras#, cas#, we#, cke, odt ci 1.0 2.0 pf 1 delta input capacitance: ba1?ba0, a0?a13 (a12 x16), cs#, ras#, cas#, we#, cke, odt cdi ? 0.25 pf 2 input/output capacitance: dqs, dqs, dm, nf cio 2.5 4.0 pf 1, 4 delta input/output capaci tance: dqs, dqs, dm, nf cdio ? 0.5 pf 3
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 113 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram i dd specifications and conditions i dd specifications and conditions table 45: ddr2 i dd specifications and conditions notes: 1?7; notes appear on page 114 parameter/condition sym config -25e -25 -3e -3 -37e -5e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is hi g h, cs# is hi g h between valid commands; address bus inputs are switching; data bus inputs are switching i dd 0 x4, x8 100 100 90 90 80 80 ma x16 135 135 120 120 110 110 operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (idd), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is hi g h, cs# is hi g h between valid commands; address bu s inputs are switching; data pattern is same as i dd 4w i dd 1 x4, x8 115 115 105 105 95 90 ma x16 165 165 150 150 135 130 precharge power-down current: all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stab le; data bus inputs are floating i dd 2p x4, x8, x16 7 7 7 7 7 7 ma precharge quiet standby current: all banks idle; t ck = t ck (i dd ); cke is hi g h, cs# is hi g h; other control and address bus inpu ts are stable; data bus inputs are floating i dd 2q x4, x8 50 50 45 45 40 35 ma x16 656555554540 precharge standby current: all banks idle; t ck = t ck (i dd ); cke is hi g h, cs# is hi g h; other control and address bus inputs are switching; data bus inputs are switching i dd 2n x4, x8 55 55 50 50 45 40 ma x16 707060605045 active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd 3p fast pdn exit mr[12] = 0 40 40 35 35 30 25 ma slow pdn exit mr[12] = 1 12 12 12 12 12 12 active standby current: all banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is hi g h, cs# is hi g h between valid commands; other control and address bus inpu ts are switching; data bus inputs are switching i dd 3n x4, x8 70 70 65 65 55 45 ma x16 757570706050 operating burst write current: all banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is hi g h, cs# is hi g h between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w x4, x8 195 195 170 170 140 115 ma x16 295 295 250 250 205 160 operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is hi g h, cs# is hi g h between valid commands; address bu s inputs are switching; data bus inputs are switching i dd 4r x4, x8 205 205 180 180 145 115 ma x16 275 275 235 235 195 155 burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is hi g h, cs# is hi g h between valid comma nds; other control and address bus inputs are sw itching; data bus inputs are switching i dd 5 x4, x8 230 230 180 180 170 165 ma x16 230 230 185 185 175 170
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 114 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram i dd specifications and conditions notes: 1. i dd specifications are tested after the device is properly initialized. 0c t c +85c. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v dd l = +1.8v 0.1v, v ref = v dd q/2. ?37v v dd q = +1.9v 0.1v, v dd l = +1.9v 0.1. 2. input slew rate is specified by ac para metric test conditions (table 46 on page 115). 3. i dd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs#, rdqs, rdqs#, ldqs, ldqs#, udqs, and udqs#. i dd values must be met with all comb inations of emr bits 10 and 11. 5. definitions for i dd conditions: 6. i dd 1, i dd 4r, and i dd 7 require a12 in emr1 to be enabled during testing. 7. the following i dd s must be derated (i dd limits increase) on it-opt ion devices when operated outside of the range 0c t c 85c: self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd 6 x4, x8, x16 777777 ma i dd 6l 333333 operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is hi g h, cs# is hi g h between valid commands; address bus inputs are stable during deselects; data bus inputs are switching (see table 47 on page 115 for details) i dd 7 x4, x8 300 300 240 240 225 220 ma x16 370 370 350 340 340 340 low v in v il ( ac ) max hi g h v in v ih ( ac ) min stable inputs stable at a hi g h or low level floating inputs at v ref = v dd q/2 switching inputs changing between hi g h and low every other clock cycle (once per two clocks) for address and control signals switching inputs changing between hi g h and low every other data transfer (once per clock) for dq signals, not including masks or strobes when t c 0c i dd 2p and i dd 3p (slow) must be derated by 4 percent; i dd 4r and i dd 5w must be derated by 2 percent; and i dd 6 and i dd 7 must be derated by 7 percent when t c 85c i dd 0, i dd 1, i dd 2n, i dd 2q, i dd 3n, i dd 3p (fast), i dd 4r, i dd 4w, and i dd 5w must be derated by 2 percent; i dd 2p must be derated by 20 percent; i dd 3pslow must be derated by 30 percent; and i dd 6 must be derated by 80 percent (i dd 6 will increase by this amount if t c < 85c and the 2x refres h option is still enabled) table 45: ddr2 i dd specifications and conditions (continued) notes: 1?7; notes appear on page 114 parameter/condition sym config -25e -25 -3e -3 -37e -5e units
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 115 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram i dd 7 conditions i dd 7 conditions the detailed timings are shown below for i dd 7. changes will be required if timing parameter changes are made to th e specification. where general i dd parameters in table 46 on page 115 conflict with pattern requirements of table 47, then table 47 requirements take precedence. notes: 1. a = active; ra = read auto precharge; d = deselect. 2. all banks are being in terleaved at minimum t rc (i dd ) without violating t rrd (i dd ) using a bl = 4. 3. control and address bus inputs are stable during deselects. 4. i out = 0ma. table 46: general i dd parameters i dd parameter -25e -25 -3e -3 -37e -5e units cl (i dd ) 564543 t ck t rcd (i dd ) 12.51512151515ns t rc (i dd ) 57.56057606055ns t rrd (i dd ) - x4/x8 (1kb) 7.57.57.57.57.57.5ns t rrd (i dd ) - x16 (2kb) 10 10 10 10 10 10 ns t ck (i dd ) 2.5 2.5 3 3 3.75 5 ns t ras min (i dd ) 45 45 45 45 45 40 ns t ras max (i dd ) 70,000 70,000 70,000 70, 000 70,000 70,000 ns t rp (i dd ) 12.51512151515ns t rfc (i dd ) 105 105 105 105 105 105 ns t faw (1kb) (i dd ) 35 35 37.5 37.5 37.5 37.5 ns t faw (2kb) (i dd ) 45 45 50 50 50 50 ns table 47: i dd 7 timing patterns (4-bank) all bank interleave read operation speed grade i dd 7 timing patterns for x4/x8/x16 -5e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d -37e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -3 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d -3e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d -25 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d d -25e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 116 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications ac operating specifications table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds (sheet 1 of 6) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -3e -3 -37e -5e units notes parameter symbol min max min max min max min max clock clock cycle time cl = 5 t ck av g (5) 3,0008,0003,0008,000????ps16, 22, 36, 38 cl = 4 t ck av g (4) 3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000 ps cl = 3 t ck av g (3) ? ? 5,000 8,000 5,000 8,000 5,000 8,000 ps ck high-level width t ch av g 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck 45 ck low-level width t cl av g 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck half clock period t hp min ( t ch, t cl) min ( t ch, t cl) min ( t ch, t cl) min ( t ch, t cl) ps 46 clock (absolute) absolute t ck t ck abs t ck av g (min) + t jit per (min) t ck av g (max) + t jit per (max) t ck av g min) + t jit per (min) t ck av g (max) + t jit per (max) t ck av g ( min) + t jit per (min) t ck av g ( max) + t jit per (max) t ck av g ( min) + t jit per (min) t ck av g (max) + t jit per (max) ps absolute ck high- level width t ch abs t ck av g (min) * t ch av g (min) + t jit dty (min) t ck av g (max) * t ch av g (max) + t jit dty (max) t ck av g (min) * t ch av g (min) + t jit dty (min) t ck av g (max) * t ch av g (max) + t jit dty (max) t ck av g (min) * t ch av g (min) + t jit dty (min) t ck av g (max) * t ch av g (max) + t jit dty (max) t ck av g (min) * t ch av g (min) + t jit dty (min) t ck av g (max) * t ch av g (max) + t jit dty (max) ps absolute ck low- level width t cl abs t ck av g (min) * t cl av g (min) + t jit dty (min) t ck av g (max) * t cl av g (max) + t jit dty (max) t ck av g (min) * t cl av g (min) + t jit dty (min) t ck av g (max) * t cl av g (max) + t jit dty (max) t ck av g (min) * t cl av g (min) + t jit dty (min) t ck av g (max) * t cl av g (max) + t jit dty (max) t ck av g (min) * t cl av g (min) + t jit dty (min) t ck av g (max) * t cl av g (max) + t jit dty (max) ps clock jitter clock jitter ? period t jit per ?125 125 ?125 125 ?125 125 ?125 125 ps 39 clock jitter ? half period t jit duty ?125 125 ?125 125 ?125 125 ?150 150 ps 40 clock jitter ? cycle to cycle t jit cc 250 250 250 250 ps 41 cumulative jitter error, 2 cycles t err 2per ?175 175 ?175 175 ?175 175 ?175 175 ps 42 cumulative jitter error, 3 cycles t err 3per ?225 225 ?225 225 ?225 225 ?225 225 ps 42 cumulative jitter error, 4 cycles t err 4per ?250 250 ?250 250 ?250 250 ?250 250 ps 42 cumulative jitter error, 5 cycles t err 5per ?250 250 ?250 250 ?250 250 ?250 250 ps 42, 48 cumulative jitter error, 6?10 cycles t err 6- 10per ?350 350 ?350 350 ?350 350 ?350 350 ps 42, 48 cumulative jitter error, 11?50 cycles t err 11- 50per ?450 450 ?450 450 ?450 450 ?450 450 ps 42
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 117 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications data dq hold skew factor t qhs ? 340 ? 340 ? 400 ? 450 ps 47 dq output access time from ck/ck# t ac -450 +450 -450 +450 -500 +500 -600 +600 ps 34, 43 data-out high-z window from ck/ ck# t hz t ac (max) t ac (max) t ac (max) t ac (max) ps 8, 9, 43 dqs low-z window from ck/ck# t lz 1 t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) ps 8, 10, 43 dq low-z window from ck/ck# t lz 2 2 * t ac (min) t ac (max) 2 * t ac (min) t ac (max) 2 * t ac (min) t ac (max) 2 * t ac (min) t ac (max) ps 8, 10, 43 dq and dm input setup time relative to dqs t ds a 300 300 350 400 ps 7, 15, 19 dq and dm input hold time relative to dqs t dh a 300 300 350 400 ps 7, 15, 19 dq and dm input setup time relative to dqs t ds b 100 100 100 150 ps 7, 15, 19 dq and dm input hold time relative to dqs t dh b 175 175 225 275 ps 7, 15, 19 dq and dm input pulse width (for each input) t dipw 0.35 0.35 0.35 0.35 t ck 37 data hold skew factor t qhs 340 340 400 450 ps 47 dq?dqs hold, dqs to first dq to go nonvalid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs ps 15, 17, 47 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 15, 17 table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds (sheet 2 of 6) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -3e -3 -37e -5e units notes parameter symbol min max min max min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 118 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications data strobe dqs input-high pulse width t dqsh 0.35 0.35 0.35 0.35 t ck 37 dqs input-low pulse width t dqsl 0.35 0.35 0.35 0.35 t ck 37 dqs output access time from ck/ck# t dqsck ?400 +400 ?400 +400 ?450 +450 ?500 +500 ps 34, 43 dqs falling edge to ck rising ? setup time t dss 0.2 0.2 0.2 0.2 t ck 37 dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 0.2 0.2 t ck 37 dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 240 240 300 350 ps 15, 17 dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck 33, 34, 37, 43 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 33, 34, 37, 43 write preamble setup time t wpres 0 0 0 0 ps 12, 13 dqs write preamble t wpre 0.35 0.35 0.25 0.25 t ck 37 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 11, 37 positive dqs latching edge to associated clock edge t dqss ?0.25 0.25 ?0.25 0.25 ?0.25 0.25 ?0.25 0.25 t ck 37 write command to first dqs latching transition wl - t dqss wl + t dqss wl - t dqss wl + t dqss wl - t dqss wl + t dqss wl - t dqss wl + t dqss t ck table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds (sheet 3 of 6) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -3e -3 -37e -5e units notes parameter symbol min max min max min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 119 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications command and address address and control input pulse width for each input t ipw 0.6 0.6 0.6 0.6 t ck 37 address and control input setup time t is a 400 400 500 600 ps 6, 19 address and control input hold time t ih a 400 400 500 600 ps 6, 19 address and control input setup time t is b 200 200 250 350 ps 6, 19 address and control input hold time t ih b 275 275 375 475 ps 6, 19 cas# to cas# command delay t ccd 2 2 2 2 t ck 37 active-to-active (same bank) command t rc 54 55 55 55 ns 31, 37 active bank a to active bank b command t rrd (x4, x8) 7.5 7.5 7.5 7.5 ns 25, 37 t rrd (x16) 10 10 10 10 ns 25, 37 active-to-read or write delay t rcd12151515ns37 4-bank activate period t faw (x4, x8) 37.5 37.5 37.5 37.5 ns 28, 37 4-bank activate period t faw (x16) 50 50 50 50 ns 28, 37 active-to- prechar g e command t ras 40 70,000 40 70,000 40 70,000 40 70,000 ns 18, 31, 37 internal read-to- prechar g e command delay t rtp 7.5 7.5 7.5 7.5 ns 21, 25, 37 write recovery time t wr 15 15 15 15 ns 25, 37 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp t wr + t rp t wr + t rp ns 20 internal write-to- read command delay t wtr 7.5 7.5 7.5 10 ns 25, 37 prechar g e command period t rp 12 15 15 15 ns 29, 37 prechar g e all command period t rpa t rp + t ck t rp + t ck t rp + t ck t rp + t ck ns 29 load mode command cycle time t mrd 2 2 2 2 t ck 37 table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds (sheet 4 of 6) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -3e -3 -37e -5e units notes parameter symbol min max min max min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 120 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications refresh cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih ns 26 refresh-to-active or refresh-to- refresh command interval t rfc 105 70,000 105 70,000 105 70,000 105 70,000 ns 14, 37 average periodic refresh interval (commercial) t refi 7.8 7.8 7.8 7.8 s 14, 37 average periodic refresh interval (industrial) t refi it 3.9 3.9 3.9 3.9 s 14, 37 self refresh exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 200 200 t ck 37 exit self refresh timing reference t isxr t is t is t is t is ps 6, 27 odt odt turn-on delay t aond22222222 t ck 37 odt turn-on t aon t ac (min) t ac (max) + 700 t ac (min) t ac (max) + 700 t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1000 ps 23, 43 odt turn-off delay t aofd 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 t ck 35, 37 odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps 24, 44 odt turn-on (power- down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power- down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 3 3 3 t ck 37 odt power-down exit latency t axpd8888 t ck 37 odt enable from mrs command t mod12121212ns37, 49 table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds (sheet 5 of 6) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -3e -3 -37e -5e units notes parameter symbol min max min max min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 121 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications power-down exit active power- down to read command, mr[12] = 0 t xard2222 t ck 37 exit active power- down to read command, mr[12] = 1 t xards 7 - al 7 - al 6 - al 6 - al t ck 37 exit precharge power-down to any non-read command t xp2222 t ck 37 cke min hi g h/low time t cke 3 3 3 3 t ck 32, 37 table 48: ac operating conditions for -3e, -3, -37e, and -5e speeds (sheet 6 of 6) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -3e -3 -37e -5e units notes parameter symbol min max min max min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 122 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications table 49: ac operating conditions for -25e and -25 speeds (sheet 1 of 4) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -25e -25 units notes parameter symbol min max min max clock clock cycle time cl = 6 t ck av g (6) n/a n/a 2,500 8,000 ps 16, 22, 36, 38 cl = 5 t ck av g (5) 2,500 8,000 3,000 8,000 ps cl = 4 t ck av g (4) 3,750 8,000 ? ? ps ck high-level width t ch av g 0.48 0.52 0.48 0.52 t ck 45 ck low-level width t cl av g 0.48 0.52 0.48 0.52 t ck 45 half-clock period t hp min ( t ch, t cl) min ( t ch, t cl) ps 46 absolute t ck t ck abs t ck av g (min) + t jit per(min) t ck av g (max) + t jit per(max) t ck av g (min) + t jit per(min) t ck av g (max) + t jit per(max) ps absolute ck high-level width t ch abs t ck av g (min) * t ch av g (min) + t jit dty(min) t ck av g (max) * t ch av g (max) + t jit dty(max) t ck av g (min) * t ch av g (min) + t jit dty(min) t ck av g (max) * t ch av g (max) + t jit dty(max) ps absolute ck low-level width t cl abs t ck av g (min) * t cl av g (min) + t jit dty(min) t ck av g (max) * t cl av g (max) + t jit dty(max) t ck av g (min) * t cl av g (min) + t jit dty(min) t ck av g (max) * t cl av g (max) + t jit dty(max) ps clock jitter clock jitter ? period t jit per ?100 100 ?100 100 ps 39 clock jitter ? half period t jit duty ?100 100 ?100 100 ps 40 clock jitter ? cycle to cycle t jit cc 200 200 ps 41 cumulative jitter error, 2 cycles t err 2per ?150 150 ?150 150 ps 42 cumulative jitter error, 3 cycles t err 3per ?175 175 ?175 175 ps 42 cumulative jitter error, 4 cycles t err 4per ?200 200 ?200 200 ps 42 cumulative jitter error, 5 cycles t err 5per ?200 200 ?200 200 ps 42, 48 cumulative jitter error, 6?10 cycles t err 6- 10per ?300 300 ?300 300 ps 42, 48 cumulative jitter error, 11?50 cycles t err 11-50per ?450 450 ?450 450 ps 42
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 123 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications data dq output access time from ck/ck# t ac ?400 +400 ?400 +400 ps 34, 43 data-out high-z window from ck/ck# t hz t ac (max) t ac (max) ps 8, 9, 43 dqs low-z window from ck/ck# t lz 1 t ac (min) t ac (max) t ac (min) t ac (max) ps 8, 10, 43 dq low-z window from ck/ck# t lz 2 2 * t ac (min) t ac (max) 2 * t ac (min) t ac (max) ps 8, 10, 43 dq and dm input setup time relative to dqs t ds a 250 250 ps 15, 19 dq and dm input hold time relative to dqs t dh a 250 250 ps 15, 19 dq and dm input setup time relative to dqs t ds b 50 50 ps 15, 19 dq and dm input hold time relative to dqs t dh b 125 125 ps 15, 19 dq and dm input pulse width (for each input) t dipw 0.35 0.35 t ck 37 data hold skew factor t qhs 300 300 ps 47 dq?dqs hold from dqs t qh t hp - t qhs t hp - t qhs ps 15, 17, 47 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq ns 15, 17 data strobe dqs input-high pulse width t dqsh 0.35 0.35 t ck 37 dqs input-low pulse width t dqsl 0.35 0.35 t ck 37 dqs output access time from ck/ck# t dqsck ?350 +350 ?350 +350 ps 34, 43 dqs falling edge to ck rising ? setup time t dss 0.2 0.2 t ck 37 dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 t ck 37 dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 200 200 ps 15, 17 dqs read preamble t rpre0.91.10.91.1 t ck 33, 34, 37, 43 dqs read postamble t rpst0.40.60.40.6 t ck 33, 34, 37, 43 write preamble setup time t wpres 0 0 ps 12, 13 dqs write preamble t wpre 0.35 0.35 t ck 37 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 11, 37 positive dqs latching edge to associated clock edge t dqss ?0.25 +0.25 ?0.25 +0.25 t ck 37 write command to fi rst dqs latching transition wl - t dqss wl + t dqss wl - t dqss wl + t dqss t ck table 49: ac operating conditions for -25e and -25 speeds (sheet 2 of 4) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -25e -25 units notes parameter symbol min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 124 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications command and address address and control input pulse width for each input t ipw 0.6 0.6 t ck 37 address and control input setup time t is a 375 375 ps 19 address and control input hold time t ih a 375 375 ps 19 address and control input setup time t is b 175 175 ps 19 address and control input hold time t ih b 250 250 ps 19 cas# to cas# command delay t ccd 2 2 t ck 37 active-to-active (same bank) command t rc 55 55 ns 31, 37 active bank a to active bank b command t rrd (x4, x8) 7.5 7.5 ns 25, 37 t rrd (x16) 10 10 ns 25, 37 active-to-read or write delay t rcd 12.5 15 ns 37 4-bank activate period t faw (1k page) 37.5 37.5 ns 28, 37 4-bank activate period t faw (2k page) 50 50 ns 28, 37 active-to-prechar g e command t ras 45 70,000 45 70,000 ns 18, 31, 37 internal read-to-prechar g e command delay t rtp 7.5 7.5 ns 21, 25, 37 write recovery time t wr 15 15 ns 25, 37 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns 20 internal write-to-r ead command delay t wtr 7.5 10 ns 25, 37 prechar g e command period t rp 12.5 15 ns 29, 37 prechar g e all command period t rpa t rp + t ck t rp + t ck ns 29 load mode command cycle time t mrd 2 2 t ck 37 refresh cke low to ck, ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih ns 26 refresh-to-active or refresh-to- refresh command interval t rfc 105 70,000 105 70,000 ns 14, 37 average periodic refresh interval t refi 7.8 7.8 s 14, 37 average periodic refresh interval (industrial) t refi it 3.9 3.9 s 14, 37 self refresh exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 t ck 37 exit self refresh timing reference t isxr t is t is ps 6, 27 table 49: ac operating conditions for -25e and -25 speeds (sheet 3 of 4) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -25e -25 units notes parameter symbol min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 125 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram ac operating specifications odt odt turn-on delay t aond2222 t ck 37 odt turn-on t aon t ac (min) t ac (max) + 700 t ac (min) t ac (max) + 700 ps 23, 43 odt turn-off delay t aofd2.52.52.52.5 t ck 35, 37 odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps 24, 44 odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 3 t ck 37 odt power-down exit latency t axpd 10 10 t ck 37 odt enable from mrs command t mod 12 12 ns 37, 49 power-down exit active power-down to read command, mr[12] = 0 t xard 2 2 t ck 37 exit active power-down to read command, mr[12] = 1 t xards 8 - al 8 - al t ck 37 exit precharge power-down to any non- read command t xp 2 2 t ck 37 cke minimum hi gh/low time t cke 3 3 t ck 32, 37 table 49: ac operating conditions for -25e and -25 speeds (sheet 4 of 4) notes: 1?5; notes appear on page 126; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -25e -25 units notes parameter symbol min max min max
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 126 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram notes notes 1. all voltages are referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. odt is disabled for all measurements that are not odt-specific. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environ- ment and parameter specifications are guar anteed for the specified ac input levels under normal use conditions. the slew rate for the input signals used to test the device is 1.0 v/ns for signals in the range between v il ( ac ) and v ih ( ac ). slew rates other than 1.0 v/ns may require the timing parameters to be derated as specified. 5. the ac and dc input level specifications are as defined in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as th e signal does not ring back above [below] the dc input low [high] level). 6. there are two sets of values listed for command/address: t is a , t ih a and t is b , t ih b . the t is a , t ih a values (for reference only) are equivalent to the baseline values of t is b , t ih b at v ref when the slew rate is 1 v/ns. the baseline values, t is b , t ih b , are the jedec- defined values, referenced from the logic trip points. t is b is referenced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal, while t ih b is referenced from v il ( dc ) for a rising signal and v ih ( dc ) for a falling signal. if the command/address slew rate is not equal to 1 v/ns, then the baseline values must be derated by adding the values from tables 26 and 27 on page 89. 7. the values listed are for the differential dqs strobe (dqs and dqs#) with a differen- tial slew rate of 2 v/ns (1 v/ns for each signal). there are two sets of values listed: t ds a , t dh a and t ds b , t dh b . the t ds a , t dh a values (for reference only) are equivalent to the baseline values of t ds b , t dh b at v ref when the slew rate is 2 v/ns, differentially. the baseline values, t ds b , t dh b , are the jedec-defined values, referenced from the logic trip points. t ds b is referenced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal, while t dh b is referenced from v il ( dc ) for a rising signal and v ih ( dc ) for a fall- ing signal. if the differential dqs slew rate is not equal to 2 v/ns, then the baseline val- ues must be derated by adding the values from tables 28 and 29 on pages 94?95. if the dqs differential strobe feature is not enab led, then the dqs strobe is single-ended, the baseline values not applicable, and timi ng is not referenced to the logic trip points. single-ended dqs data timing is referenced to dqs crossing v ref . the correct timing values for a single-ended dqs strobe are listed in tables 30?33 on pages 96?97; listed values are already derate d for slew rate variations and can be used directly from the table. 8. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 9. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. output (v out ) referen c e point 25 v tt = v dd q/2
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 127 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram notes 11. the intent of the ?don?t care? state after completion of the postamble is that the dqs- driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ih [ dc ] min), then it must not transition low (below v ih [ dc ]) prior to t dqsh (min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms (commercial) or 32ms (industrial). this equates to an aver- age refresh rate of 7.8125s (commercial) or 3.9607s (industrial). however, a refresh command must be asserted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8,192 refresh commands must be issued every 64ms (commercial) or 32ms (industrial). 15. referenced to each output group: x4 = dqs with dq0?dq3; x8 = dqs with dq0?dq7; x16 = ldqs with dq0?dq7; and udqs with dq8?dq15. 16. ck and ck# input slew rate is referenced at 1 v/ns (2 v/ns if measured differentially). 17. the data valid window is derive d by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle and a practical data valid window can be derived. 18. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied since t ras lockout feature is supported in ddr2 sdram. 19. v il /v ih ddr2 overshoot/undershoot. see ?ac overshoot/undershoot specification? on page 105. 20. t dal = (nwr) + ( t rp/ t ck). each of these terms, if not already an integer, should be rounded up to the next integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11, 10, 9]. for example, -37e at t ck = 3.75ns with t wr programmed to four clocks would have t dal = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks. 21. the minimum internal read to precharge time. this is the time from the last 4-bit prefetch begins to when the precharge co mmand can be issued. a 4-bit prefetch is when the read command internally latches the read so that data will output cl later. this parameter is only applicable when t rtp / (2 x t ck) > 1, such as frequencies faster than 533 mhz when t rtp = 7.5ns. if t rtp / (2 x t ck) 1, then equation al + bl/ 2 applies. t ras (min) also has to be satisfied as well. the ddr2 sdram will automat- ically delay the internal precharge command until t ras (min) has been satisfied. 22. operating frequency is only allowed to change during self refresh mode (see figure 54 on page 71), precharge power-down mode, or system reset condition (see ?reset function? on page 72). ssc allows for smal l deviations in operating frequency, pro- vided the ssc guidelines are satisfied. 23. odt turn-on time t aon (min) is when the device leaves high-z and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond. 24. odt turn-off time t aof (min) is when the device star ts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high-z. both are measured from t aofd. 25. this parameter has a two cloc k minimum requirement at any t ck.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 128 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram notes 26. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. see ?reset function? on page 72. 27. t isxr is equal to t is and is used for cke setup time during self refresh exit, as shown in figure 43 on page 62. 28. no more than four bank-active commands may be issued in a given t faw (min) period. t rrd (min) restriction still applies. the t faw (min) parameter applies to all 8-bank ddr2 devices, regardless of the number of banks already open or closed. 29. t rpa timing applies when the precharge (a ll) command is issued, regardless of the number of banks already open or closed. if a single-bank precharge command is issued, t rp timing applies. t rpa (min) applies to all 8-bank ddr2 devices. 30. n/a. 31. this is applicable to read cycles only. write cycles generally require additional time due to t wr during auto precharge. 32. t cke (min) of three clocks means cke must be registered on three consecutive posi- tive clock edges. cke must remain at the va lid input level the entire time it takes to achieve the three clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 x t ck + t ih. 33. this parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving ( t rpst) or beginning to drive ( t rpre). 34. when dqs is used single-ended, th e minimum limit is reduced by 100ps. 35. the half-clock of t aofd?s 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47, for t aof (min) and 2.5 + 0.03, or 2.53, for t aof (max). 36. the clock?s t ck avg is the average clock over any 200 consecutive clocks and t ck avg (min) is the smallest clock ra te allowed, except a deviatio n due to allowed clock jitter. input clock jitter is allowed provided it does not exceed values specified. also, the jit- ter must be of a random gaussian distribution in nature. 37. the inputs to the dram must be aligned to the associated clock; that is, the actual clock that latches it in. however, the input timing (in ns) references to the t ck avg when determining the required number of clocks. the following input parameters are determined by taking the specified percentage times the t ck avg rather than t ck: t ipw, t dipw, t dqss, t dqsh, t dqsl, t dss, t dsh, t wpst, and t wpre. 38. spread spectrum is not included in the ji tter specification values. however, the input clock can accommodate spread spectrum at a sweep rate in the range 20?60 khz with additional one percent of t ck avg as a long-term jitter co mponent; however, the spread spectrum may not use a clock rate below t ck avg(min) or above t ck avg(max) . 39. the period jitter ( t jit per ) is the maximum deviation in the clock period from the aver- age or nominal clock allowed in either the positive or negative direction. jedec spec- ifies tighter jitter numbers during dll lock ing time. during dll lock time, the jitter values should be 20 percent less than noted in the table (dll locked). 40. the half-period jitter ( t jit dty ) applies to either the high pulse of clock or the low pulse of clock; however, the two cumulatively can not exceed t jit per . 41. the cycle-to-cycle jitter ( t jit cc ) is the amount the clock pe riod can deviate from one cycle to the following cycle. jedec specifies tighter jitter numbers during dll locking time. during dll lock time, the jitter values should be 20 percent less than noted in the table (dll locked). 42. the cumulative jitter error ( t err nper ), where n is 2, 3, 4, 5, 6?10, or 11?50, is the amount of clock time allowe d to consecutively accumula te away from the average clock over any number of clock cycles.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 129 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram notes 43. the dram output timing is aligned to the nominal or average clock. most output parameters must be derated by the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. the following parameters are required to be derated by subtracting t err 5per (max): t ac (min), t dqsck (min), t lz dqs (min), t lz dq (min), t aon (min); while these following parameters are required to be derated by subtracting t err 5per (min): t ac (max), t dqsck (max), t hz (max), t lz dqs (max), t lz dq (max), t aon (max). the parameter t rpre (min) is der- ated by subtracting t jit per (max), while t rpre (max), is derated by subtracting t jit per (min). the parameter t rpst (min) is derated by subtracting t jit dty (max), while t rpst (max), is derated by subtracting t jit dty (min). 44. half-clock output parameters must be derated by the actual t err 5 per and t jit dty when input clock jitter is present; this will result in each parameter becoming larger. the parameter t aof (min) is required to be derated by subtracting both t err 5 per (max) and t jit dty (max). the parameter t aof (max) is required to be derated by subtracting both t err 5 per (min) and t jit dty (min). 45. min( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time driven to the device. the clock?s half period must also be of a gaussian dis- tribution; t ch avg and t cl avg must be met with or with out clock jitter and with or without duty cycle jitter. t ch avg and t cl avg are the average of any 200 consecutive ck falling edges. 46. t hp (min) is the lesser of t cl and t ch actually applied to the device ck and ck# inputs; thus, t hp (min) the lesser of t cl abs (min) and t ch abs (min). 47. t qh = t hp - t qhs; the worst case t qh would be the smaller of t cl abs (max) or t ch abs (max) times t ck abs (min) - t qhs. minimizing the amount of t ch avg offset and value of t jit dty will provide a larger t qh, which in turn will provide a larger valid data out window. 48. jedec specifies using t err 6?10 per when derating clock-related output timing (notes 43?44). micron requires less derating by allowing t err 5 per to be used. 49. requires 8 t ck for backwards compatibility.
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 130 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram package dimensions package dimensions figure 88: 84-ball fbga package ? 12mm x 12.5mm (x16) note: all dimensions are in millimeters. 0.80 0.05 0.10 c c mold c ompound: epoxy novala c s older ball material: 9 6 .5 % s n, 3 % a g , 0.5 % c u s older ball pad: ?0.33 non s older ma s k defined s ub s trate material: pla s ti c laminate 5. 6 0 11.20 ball a1 id ball a1 ball a1 id 0.80 typ 6 .00 0.05 3.20 12.00 0.10 6 .40 ball a9 s eating plane 12.50 0.10 6 .25 0.05 0.80 typ 84x ?0.45 c l c l s older ball diameter refer s to po s t-reflow c ondition. 1.20 max 0.155 0.013 1.80 0.05 c tr
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 131 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram package dimensions figure 89: 84-ball fbga package ? 10mm x 12.5mm (x16) note: all dimensions are in millimeters. ball a1 id 1.20 max ball a9 ball a1 id 0.80 typ 0.80 typ 3.20 6 .40 ball a1 10.00 0.10 5.00 0.05 s older ball diameter refer s to po s t reflow c ondition. the pre- reflow diameter i s 0.42 84x ? 0.45 s older ball material: 6 2 % s n, 3 6% p b , 2 % a g or 9 6 .5 % s n, 3 % a g , 0.5 %c u non s older ma s k defined ball pad: ? 0.33 mold c ompound: epoxy novola c s ub s trate material: pla s ti c laminate 11.20 5. 6 0 6 .25 0.05 12.50 0.10 c l c l 0.80 0.05 0.155 0.013 s eating plane c 1.80 0.05 c tr 0.10 c
pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 132 ?2004 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr2 sdram package dimensions figure 90: 60-ball fbga package ? 12mm x 10mm (x4, x8) note: all dimensions are in millimeters. 0.80 0.05 0.10 c c 0.155 0.013 mold c ompound: epoxy novala c s older ball material: 9 6 .5 % s n, 3 % a g , 0.5 % c u s older ball pad: ?0.33 non s older ma s k defined s ub s trate material: pla s ti c laminate 4.00 8.00 ball a1 id ball a1 ball a1 id 0.80 typ 6 .00 0.05 3.20 12.00 0.10 6 .40 ball a9 s eating plane 10.00 0.10 5.00 0.05 0.80 typ 6 0x ?0.45 c l c l 1.20 max 1.80 0.05 c tr s older ball diameter refer s to po s t-reflow c ondition.
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 512mb: x4, x8, x16 ddr2 sdram package dimensions pdf: 09005aef8117c18e, source: 09005aef8211b2e6 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddr2_2.fm - rev. k 8/06 en 133 ?2004 micron technology, inc. all rights reserved. figure 91: 60-ball fbga package ? 10mm x 10mm (x4, x8) note: all dimensions are in millimeters. ball a1 id 1.20 max mold c ompound: epoxy novola c s ub s trate material: pla s ti c laminate s older ball material: 6 2 % s n, 3 6% p b , 2 % a g or 9 6 .5 % s n, 3 % a g , 0.5 %c u non s older ma s k defined ball pad: ?0.33 ball a9 0.80 typ 10.00 0.10 5.00 0.05 3.20 4.00 0.80 0.05 0.155 0.013 s eating plane c 8.00 6 .40 1.80 0.05 c tr 0.10 c 6 0x ?0.45 s older ball diameter refer s to po s t reflow c ondition. the pre- reflow diameter i s 0.42 c l 10.00 0.10 ball a1 ball a1 id 0.80 typ 5.00 0.05 c l

▲Up To Search▲

Price & Availability of MT47H64M8

	To Download MT47H64M8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .